diff mbox series

[FFmpeg-devel,1/3] lavu: detect RISC-V F extension (i.e. float)

Message ID 20220914175031.162194-1-remi@remlab.net
State New
Headers show
Series RISC-V CPU detection | expand

Checks

Context Check Description
yinshiyou/make_loongarch64 success Make finished
yinshiyou/make_fate_loongarch64 success Make fate finished
andriy/make_x86 success Make finished
andriy/make_fate_x86 success Make fate finished

Commit Message

Rémi Denis-Courmont Sept. 14, 2022, 5:50 p.m. UTC
From: Rémi Denis-Courmont <remi@remlab.net>

This introduces compile-tim and run-time CPU detection on RISC-V. In
practice, I doubt that FFmpeg will ever see a RISC-V CPU without the F
extension, and if it does, it probably won't have run-time detection.
So the flag is essentially always set.

But as things stand, checkasm wants it that way, and we are nowhere
near running short on CPU flag bits on that platform.
---
 libavutil/cpu.c           |  4 ++++
 libavutil/cpu.h           |  3 +++
 libavutil/cpu_internal.h  |  1 +
 libavutil/riscv/Makefile  |  1 +
 libavutil/riscv/cpu.c     | 44 +++++++++++++++++++++++++++++++++++++++
 tests/checkasm/checkasm.c |  2 ++
 6 files changed, 55 insertions(+)
 create mode 100644 libavutil/riscv/Makefile
 create mode 100644 libavutil/riscv/cpu.c

Comments

Lynne Sept. 14, 2022, 7:28 p.m. UTC | #1
Sep 14, 2022, 19:50 by remi@remlab.net:

> From: Rémi Denis-Courmont <remi@remlab.net>
>
> This introduces compile-tim and run-time CPU detection on RISC-V. In
> practice, I doubt that FFmpeg will ever see a RISC-V CPU without the F
> extension, and if it does, it probably won't have run-time detection.
> So the flag is essentially always set.
>
> But as things stand, checkasm wants it that way, and we are nowhere
> near running short on CPU flag bits on that platform.
> ---
>  libavutil/cpu.c           |  4 ++++
>  libavutil/cpu.h           |  3 +++
>  libavutil/cpu_internal.h  |  1 +
>  libavutil/riscv/Makefile  |  1 +
>  libavutil/riscv/cpu.c     | 44 +++++++++++++++++++++++++++++++++++++++
>  tests/checkasm/checkasm.c |  2 ++
>  6 files changed, 55 insertions(+)
>  create mode 100644 libavutil/riscv/Makefile
>  create mode 100644 libavutil/riscv/cpu.c
>
> diff --git a/libavutil/cpu.c b/libavutil/cpu.c
> index 0035e927a5..6e9b8c5f58 100644
> --- a/libavutil/cpu.c
> +++ b/libavutil/cpu.c
> @@ -62,6 +62,8 @@ static int get_cpu_flags(void)
>  return ff_get_cpu_flags_arm();
>  #elif ARCH_PPC
>  return ff_get_cpu_flags_ppc();
> +#elif ARCH_RISCV
> +    return ff_get_cpu_flags_riscv();
>  #elif ARCH_X86
>  return ff_get_cpu_flags_x86();
>  #elif ARCH_LOONGARCH
> @@ -178,6 +180,8 @@ int av_parse_cpu_caps(unsigned *flags, const char *s)
>  #elif ARCH_LOONGARCH
>  { "lsx",      NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_LSX      },    .unit = "flags" },
>  { "lasx",     NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_LASX     },    .unit = "flags" },
> +#elif ARCH_RISCV
> +        { "float",    NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_F        },    .unit = "flags" },
>  #endif
>  { NULL },
>  };
> diff --git a/libavutil/cpu.h b/libavutil/cpu.h
> index 9711e574c5..71ae70bcbd 100644
> --- a/libavutil/cpu.h
> +++ b/libavutil/cpu.h
> @@ -78,6 +78,9 @@
>  #define AV_CPU_FLAG_LSX          (1 << 0)
>  #define AV_CPU_FLAG_LASX         (1 << 1)
>  
> +// RISC-V Vector extension
> +#define AV_CPU_FLAG_F            (1 << 0)
>

Can you prefix that with RV (FLAG_RVF) like the function?
Rémi Denis-Courmont Sept. 14, 2022, 7:43 p.m. UTC | #2
Le keskiviikkona 14. syyskuuta 2022, 22.28.01 EEST Lynne a écrit :
> Sep 14, 2022, 19:50 by remi@remlab.net:
> > From: Rémi Denis-Courmont <remi@remlab.net>
> > 
> > This introduces compile-tim and run-time CPU detection on RISC-V. In
> > practice, I doubt that FFmpeg will ever see a RISC-V CPU without the F
> > extension, and if it does, it probably won't have run-time detection.
> > So the flag is essentially always set.
> > 
> > But as things stand, checkasm wants it that way, and we are nowhere
> > near running short on CPU flag bits on that platform.
> > ---
> > 
> >  libavutil/cpu.c           |  4 ++++
> >  libavutil/cpu.h           |  3 +++
> >  libavutil/cpu_internal.h  |  1 +
> >  libavutil/riscv/Makefile  |  1 +
> >  libavutil/riscv/cpu.c     | 44 +++++++++++++++++++++++++++++++++++++++
> >  tests/checkasm/checkasm.c |  2 ++
> >  6 files changed, 55 insertions(+)
> >  create mode 100644 libavutil/riscv/Makefile
> >  create mode 100644 libavutil/riscv/cpu.c
> > 
> > diff --git a/libavutil/cpu.c b/libavutil/cpu.c
> > index 0035e927a5..6e9b8c5f58 100644
> > --- a/libavutil/cpu.c
> > +++ b/libavutil/cpu.c
> > @@ -62,6 +62,8 @@ static int get_cpu_flags(void)
> > 
> >  return ff_get_cpu_flags_arm();
> >  #elif ARCH_PPC
> >  return ff_get_cpu_flags_ppc();
> > 
> > +#elif ARCH_RISCV
> > +    return ff_get_cpu_flags_riscv();
> > 
> >  #elif ARCH_X86
> >  return ff_get_cpu_flags_x86();
> >  #elif ARCH_LOONGARCH
> > 
> > @@ -178,6 +180,8 @@ int av_parse_cpu_caps(unsigned *flags, const char *s)
> > 
> >  #elif ARCH_LOONGARCH
> >  { "lsx",      NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_LSX     
> >  },    .unit = "flags" }, { "lasx",     NULL, 0, AV_OPT_TYPE_CONST, {
> >  .i64 = AV_CPU_FLAG_LASX     },    .unit = "flags" },> 
> > +#elif ARCH_RISCV
> > +        { "float",    NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_F 
> >       },    .unit = "flags" },> 
> >  #endif
> >  { NULL },
> >  };
> > 
> > diff --git a/libavutil/cpu.h b/libavutil/cpu.h
> > index 9711e574c5..71ae70bcbd 100644
> > --- a/libavutil/cpu.h
> > +++ b/libavutil/cpu.h
> > @@ -78,6 +78,9 @@
> > 
> >  #define AV_CPU_FLAG_LSX          (1 << 0)
> >  #define AV_CPU_FLAG_LASX         (1 << 1)
> > 
> > +// RISC-V Vector extension
> > +#define AV_CPU_FLAG_F            (1 << 0)
> 
> Can you prefix that with RV (FLAG_RVF) like the function?

I agree that the name is a bit unfortunate, and that's essentially because 
RISC-V is not making up cool marketing names for their ISA extensions.

But it is consistent with what other architectures do, and RVF wouldn't be. So 
I have mixed feelings here. Arguably, the correct approach would be to only 
define the flags on their respective target architectures (and leave it as just 
"F").

I guess I will change it to RVF if nobody else expresses a contradictory 
opinion.
diff mbox series

Patch

diff --git a/libavutil/cpu.c b/libavutil/cpu.c
index 0035e927a5..6e9b8c5f58 100644
--- a/libavutil/cpu.c
+++ b/libavutil/cpu.c
@@ -62,6 +62,8 @@  static int get_cpu_flags(void)
     return ff_get_cpu_flags_arm();
 #elif ARCH_PPC
     return ff_get_cpu_flags_ppc();
+#elif ARCH_RISCV
+    return ff_get_cpu_flags_riscv();
 #elif ARCH_X86
     return ff_get_cpu_flags_x86();
 #elif ARCH_LOONGARCH
@@ -178,6 +180,8 @@  int av_parse_cpu_caps(unsigned *flags, const char *s)
 #elif ARCH_LOONGARCH
         { "lsx",      NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_LSX      },    .unit = "flags" },
         { "lasx",     NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_LASX     },    .unit = "flags" },
+#elif ARCH_RISCV
+        { "float",    NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_F        },    .unit = "flags" },
 #endif
         { NULL },
     };
diff --git a/libavutil/cpu.h b/libavutil/cpu.h
index 9711e574c5..71ae70bcbd 100644
--- a/libavutil/cpu.h
+++ b/libavutil/cpu.h
@@ -78,6 +78,9 @@ 
 #define AV_CPU_FLAG_LSX          (1 << 0)
 #define AV_CPU_FLAG_LASX         (1 << 1)
 
+// RISC-V Vector extension
+#define AV_CPU_FLAG_F            (1 << 0)
+
 /**
  * Return the flags which specify extensions supported by the CPU.
  * The returned value is affected by av_force_cpu_flags() if that was used
diff --git a/libavutil/cpu_internal.h b/libavutil/cpu_internal.h
index 650d47fc96..634f28bac4 100644
--- a/libavutil/cpu_internal.h
+++ b/libavutil/cpu_internal.h
@@ -48,6 +48,7 @@  int ff_get_cpu_flags_mips(void);
 int ff_get_cpu_flags_aarch64(void);
 int ff_get_cpu_flags_arm(void);
 int ff_get_cpu_flags_ppc(void);
+int ff_get_cpu_flags_riscv(void);
 int ff_get_cpu_flags_x86(void);
 int ff_get_cpu_flags_loongarch(void);
 
diff --git a/libavutil/riscv/Makefile b/libavutil/riscv/Makefile
new file mode 100644
index 0000000000..1f818043dc
--- /dev/null
+++ b/libavutil/riscv/Makefile
@@ -0,0 +1 @@ 
+OBJS += riscv/cpu.o
diff --git a/libavutil/riscv/cpu.c b/libavutil/riscv/cpu.c
new file mode 100644
index 0000000000..6fc30f73c6
--- /dev/null
+++ b/libavutil/riscv/cpu.c
@@ -0,0 +1,44 @@ 
+/*
+ * This file is part of FFmpeg.
+ *
+ * FFmpeg is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2.1 of the License, or (at your option) any later version.
+ *
+ * FFmpeg is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with FFmpeg; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include "libavutil/cpu.h"
+#include "libavutil/cpu_internal.h"
+#include "config.h"
+
+#if HAVE_GETAUXVAL
+#include <sys/auxv.h>
+#endif
+
+#define HWCAP_RV(letter) (1ul << ((letter) - 'A'))
+
+int ff_get_cpu_flags_riscv(void)
+{
+    int ret = 0;
+#if HAVE_GETAUXVAL
+    const unsigned long hwcap = getauxval(AT_HWCAP);
+
+    if (hwcap & HWCAP_RV('F'))
+        ret |= AV_CPU_FLAG_F;
+#endif
+
+#ifdef __riscv_flen
+    ret |= AV_CPU_FLAG_F;
+#endif
+
+    return ret;
+}
diff --git a/tests/checkasm/checkasm.c b/tests/checkasm/checkasm.c
index e56fd3850e..4f6edfe6a3 100644
--- a/tests/checkasm/checkasm.c
+++ b/tests/checkasm/checkasm.c
@@ -226,6 +226,8 @@  static const struct {
     { "ALTIVEC",  "altivec",  AV_CPU_FLAG_ALTIVEC },
     { "VSX",      "vsx",      AV_CPU_FLAG_VSX },
     { "POWER8",   "power8",   AV_CPU_FLAG_POWER8 },
+#elif ARCH_RISCV
+    { "F",        "f",        AV_CPU_FLAG_F },
 #elif ARCH_MIPS
     { "MMI",      "mmi",      AV_CPU_FLAG_MMI },
     { "MSA",      "msa",      AV_CPU_FLAG_MSA },