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[FFmpeg-devel,0/3] RISC-V V swscale pixel format conversions

Message ID 12088142.O9o76ZdvQC@basile.remlab.net
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Series RISC-V V swscale pixel format conversions | expand

Message

Rémi Denis-Courmont Sept. 28, 2022, 3:29 p.m. UTC
Hello,

This adds the pixel format conversions that appear to covered by checkasm
(plus YUYV to I422 for which a patch was sent already).

RVV has no register-register interleaving/deinterleaving instructions, so this
uses strided loads or stores instead. Another option would be full register move then segmented store, but that is presumably slower.

The following changes since commit d31013166ac3727ae7c7ebbb756e1e5800bc2b40:

  lavc/pixblockdsp: RISC-V diff_pixels & diff_pixels_unaligned (2022-09-28 11:46:11 +0200)

are available in the Git repository at:

  git.remlab.net:git/ffmpeg.git rvv-swscale

for you to fetch changes up to 18edd2c3108b126fc478635ac1048db60b9d7fc4:

  sws/rgb2rgb: RISC-V 64-bit V packed YUYV/UYVY to planar 4:2:2 (2022-09-28 18:23:53 +0300)

----------------------------------------------------------------
Rémi Denis-Courmont (3):
      sws/rgb2rgb: RISC-V V shuffle_bytes_xxxx functions
      sws/rgb2rgb: RISC-V V interleaveBytes
      sws/rgb2rgb: RISC-V 64-bit V packed YUYV/UYVY to planar 4:2:2

 libswscale/rgb2rgb.c           |   2 +
 libswscale/rgb2rgb.h           |   1 +
 libswscale/riscv/Makefile      |   2 +
 libswscale/riscv/rgb2rgb.c     |  61 ++++++++++++++++
 libswscale/riscv/rgb2rgb_rvv.S | 157 +++++++++++++++++++++++++++++++++++++++++
 5 files changed, 223 insertions(+)
 create mode 100644 libswscale/riscv/Makefile
 create mode 100644 libswscale/riscv/rgb2rgb.c
 create mode 100644 libswscale/riscv/rgb2rgb_rvv.S

Comments

Lynne Sept. 29, 2022, 4:04 a.m. UTC | #1
Sep 28, 2022, 17:29 by remi@remlab.net:

> Hello,
>
> This adds the pixel format conversions that appear to covered by checkasm
> (plus YUYV to I422 for which a patch was sent already).
>
> RVV has no register-register interleaving/deinterleaving instructions, so this
> uses strided loads or stores instead. Another option would be full register move then segmented store, but that is presumably slower.
>
> The following changes since commit d31013166ac3727ae7c7ebbb756e1e5800bc2b40:
>
>  lavc/pixblockdsp: RISC-V diff_pixels & diff_pixels_unaligned (2022-09-28 11:46:11 +0200)
>
> are available in the Git repository at:
>
>  git.remlab.net:git/ffmpeg.git rvv-swscale
>
> for you to fetch changes up to 18edd2c3108b126fc478635ac1048db60b9d7fc4:
>
>  sws/rgb2rgb: RISC-V 64-bit V packed YUYV/UYVY to planar 4:2:2 (2022-09-28 18:23:53 +0300)
>
> ----------------------------------------------------------------
> Rémi Denis-Courmont (3):
>  sws/rgb2rgb: RISC-V V shuffle_bytes_xxxx functions
>  sws/rgb2rgb: RISC-V V interleaveBytes
>  sws/rgb2rgb: RISC-V 64-bit V packed YUYV/UYVY to planar 4:2:2
>
>  libswscale/rgb2rgb.c           |   2 +
>  libswscale/rgb2rgb.h           |   1 +
>  libswscale/riscv/Makefile      |   2 +
>  libswscale/riscv/rgb2rgb.c     |  61 ++++++++++++++++
>  libswscale/riscv/rgb2rgb_rvv.S | 157 +++++++++++++++++++++++++++++++++++++++++
>  5 files changed, 223 insertions(+)
>  create mode 100644 libswscale/riscv/Makefile
>  create mode 100644 libswscale/riscv/rgb2rgb.c
>  create mode 100644 libswscale/riscv/rgb2rgb_rvv.S
>

Patchset looks good. Will apply in a couple of hours.