From patchwork Thu Sep 13 03:04:05 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shiyou Yin X-Patchwork-Id: 10311 Delivered-To: ffmpegpatchwork@gmail.com Received: by 2002:a02:12c4:0:0:0:0:0 with SMTP id 65-v6csp113077jap; Wed, 12 Sep 2018 20:04:17 -0700 (PDT) X-Google-Smtp-Source: ANB0VdaBIKdpqRr2vfeIFdwlqQtSqwIcJ7X9QbbuLtJ1uwl/CNpPEFEE67XeHk1J8adLGVo7Wl58 X-Received: by 2002:adf:a4d1:: with SMTP id h17-v6mr3306356wrb.167.1536807857672; Wed, 12 Sep 2018 20:04:17 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1536807857; cv=none; d=google.com; s=arc-20160816; b=kFqC88N3U902xN/mD08SUmPfAXo+vEb8eTQSJh2q4oNKnL4nWTTEEgHJlvoFxFFaxT w+nb3mnoqeHeokOKgrSbyJywKGnp0dsY4GUO1xf6BNUdBLzl0ADBtf8ZhmCSGkNcgHHN SYv9nZnRJw2HnBTS4qyvf1nNYLGa91zz+Yy6gJZJSKhn4Nj0RlkdzJAYwAPDcaauX5xY ehtYLst8oWVGp7qelaSY1xxS1pAFxzNFFRWsWF/oM+CuVJzGArmQ5ABieAmBgpMNRGZ5 +Q4gwZp28HnWskTJK1sry1tcP5GThNEvMUYcLodAnRXMOLRj40zz5SIn83Q0EDAYAx4/ VC2g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:reply-to :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:message-id:date:to:from:delivered-to; bh=3eacd3hBTHSpo/5ilJabeTe609EZEtDDbtrt8uYmQGY=; b=F8JytWToD28G1Anja7UOds+xGaplrPi9NNaLq/2TVgy1OABpMuRAJG/pxELt0Qk6v5 W9xYNf2oYOPZWAm0EAB4yvHAPrhElb+ik0mHGy6ICl6k8PS/RZKlmO3EDnzJmoGkxHGv DHV5SyOhRrnfGw+9CVG/L2VPDVHqJlTQrojVEYAThMs3sLA5na5Bk/Yi+KpLn/MTvbYZ gm6wfRDDNX+78UNgck4mniXAP0qhc5B2dL/gxxWTRmo+V3mNMwCU7ngkEV4/XLZoJbEQ p4J+Ps+dn3roYVWYkWnhvF2xZ68vvtX0UGB2iaM8qywBUd7WAbVL4wHIWL/oaNi1GDnw EYRA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of ffmpeg-devel-bounces@ffmpeg.org designates 79.124.17.100 as permitted sender) smtp.mailfrom=ffmpeg-devel-bounces@ffmpeg.org Return-Path: Received: from ffbox0-bg.mplayerhq.hu (ffbox0-bg.ffmpeg.org. [79.124.17.100]) by mx.google.com with ESMTP id v17-v6si2482830wrp.279.2018.09.12.20.04.17; Wed, 12 Sep 2018 20:04:17 -0700 (PDT) Received-SPF: pass (google.com: domain of ffmpeg-devel-bounces@ffmpeg.org designates 79.124.17.100 as permitted sender) client-ip=79.124.17.100; Authentication-Results: mx.google.com; spf=pass (google.com: domain of ffmpeg-devel-bounces@ffmpeg.org designates 79.124.17.100 as permitted sender) smtp.mailfrom=ffmpeg-devel-bounces@ffmpeg.org Received: from [127.0.1.1] (localhost [127.0.0.1]) by ffbox0-bg.mplayerhq.hu (Postfix) with ESMTP id 4B1F468A58F; Thu, 13 Sep 2018 06:04:05 +0300 (EEST) X-Original-To: ffmpeg-devel@ffmpeg.org Delivered-To: ffmpeg-devel@ffmpeg.org Received: from mail.loongson.cn (mail.loongson.cn [114.242.206.163]) by ffbox0-bg.mplayerhq.hu (Postfix) with ESMTP id 4F2C268A57A for ; Thu, 13 Sep 2018 06:03:57 +0300 (EEST) Received: from localhost (unknown [210.45.123.188]) by mail (Coremail) with SMTP id QMiowPCxieR605lbgO0YAA--.49124S3; Thu, 13 Sep 2018 11:03:22 +0800 (CST) From: Shiyou Yin To: ffmpeg-devel@ffmpeg.org Date: Thu, 13 Sep 2018 11:04:05 +0800 Message-Id: <1536807845-8254-1-git-send-email-yinshiyou-hf@loongson.cn> X-Mailer: git-send-email 2.1.0 X-CM-TRANSID: QMiowPCxieR605lbgO0YAA--.49124S3 X-Coremail-Antispam: 1UD129KBjvJXoW3Jr13Xw1rZw4UXr13JrW8WFg_yoWfWw1kp3 48Aw4jv3WjvF4kG3WUXw1UCrW3Zr4vyFsxC3yUtF4vv34Fqr47JrWxGr97GrWYkay5tF4U Ar15ZFWakwn5GF7anT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUkqb4IE77IF4wAFF20E14v26r1j6r4UM7CY07I20VC2zVCF04k2 6cxKx2IYs7xG6rWj6s0DM7CIcVAFz4kK6r1j6r18M28lY4IEw2IIxxk0rwA2F7IY1VAKz4 vEj48ve4kI8wA2z4x0Y4vE2Ix0cI8IcVAFwI0_Gr0_Xr1l84ACjcxK6xIIjxv20xvEc7Cj xVAFwI0_Gr0_Cr1l84ACjcxK6I8E87Iv67AKxVW8Jr0_Cr1UM28EF7xvwVC2z280aVCY1x 0267AKxVW8Jr0_Cr1UM2AIxVAIcxkEcVAq07x20xvEncxIr21l5I8CrVACY4xI64kE6c02 F40Ex7xfMcIj6xIIjxv20xvE14v26r106r15McIj6I8E87Iv67AKxVWUJVW8JwAm72CE4I kC6x0Yz7v_Jr0_Gr1lF7xvr2IYc2Ij64vIr41lF7xvr2IYc2Ij64vIr40E4x8a64kEw24l c2xSY4AK67AK6r48MxAIw28IcxkI7VAKI48JMxC20s026xCaFVCjc4AY6r1j6r4UMI8I3I 0E5I8CrVAFwI0_Jr0_Jr4lx2IqxVCjr7xvwVAFwI0_JrI_JrWlx4CE17CEb7AF67AKxVWU JVWUXwCI42IY6xIIjxv20xvE14v26r1j6r1xMIIF0xvE2Ix0cI8IcVCY1x0267AKxVWUJV W8JwCI42IY6xAIw20EY4v20xvaj40_Zr0_Wr1UMIIF0xvEx4A2jsIE14v26r1j6r4UMIIF 0xvEx4A2jsIEc7CjxVAFwI0_Jr0_GrUvcSsGvfC2KfnxnUUI43ZEXa7IU8PDG7UUUUU== X-CM-SenderInfo: p1lq2x5l1r3gtki6z05rqj20fqof0/ Subject: [FFmpeg-devel] [PATCH] avcodec/mips: [loongson] fix bug of svq3-watermark failed in fate test. X-BeenThere: ffmpeg-devel@ffmpeg.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: FFmpeg development discussions and patches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: FFmpeg development discussions and patches MIME-Version: 1.0 Errors-To: ffmpeg-devel-bounces@ffmpeg.org Sender: "ffmpeg-devel" Failed case: svq3-watermark When minimum loop count of following functions are greater than parameter h passed to them, svq3-watermark failed. 1. ff_put_pixels4_8_mmi 2. ff_avg_pixels4_8_mmi 3. ff_put_pixels4_l2_8_mmi 4. ff_avg_pixels4_l2_8_mmi --- libavcodec/mips/hpeldsp_mmi.c | 112 +++++++++--------------------------------- 1 file changed, 23 insertions(+), 89 deletions(-) diff --git a/libavcodec/mips/hpeldsp_mmi.c b/libavcodec/mips/hpeldsp_mmi.c index db2fa10..e69b2bd 100644 --- a/libavcodec/mips/hpeldsp_mmi.c +++ b/libavcodec/mips/hpeldsp_mmi.c @@ -38,21 +38,13 @@ void ff_put_pixels4_8_mmi(uint8_t *block, const uint8_t *pixels, PTR_ADDU "%[pixels], %[pixels], %[line_size] \n\t" MMI_ULWC1(%[ftmp1], %[pixels], 0x00) PTR_ADDU "%[pixels], %[pixels], %[line_size] \n\t" - MMI_ULWC1(%[ftmp2], %[pixels], 0x00) - PTR_ADDU "%[pixels], %[pixels], %[line_size] \n\t" - MMI_ULWC1(%[ftmp3], %[pixels], 0x00) - PTR_ADDU "%[pixels], %[pixels], %[line_size] \n\t" - PTR_ADDI "%[h], %[h], -0x04 \n\t" + PTR_ADDI "%[h], %[h], -0x02 \n\t" MMI_SWC1(%[ftmp0], %[block], 0x00) PTR_ADDU "%[block], %[block], %[line_size] \n\t" MMI_SWC1(%[ftmp1], %[block], 0x00) PTR_ADDU "%[block], %[block], %[line_size] \n\t" - MMI_SWC1(%[ftmp2], %[block], 0x00) - PTR_ADDU "%[block], %[block], %[line_size] \n\t" - MMI_SWC1(%[ftmp3], %[block], 0x00) - PTR_ADDU "%[block], %[block], %[line_size] \n\t" "bnez %[h], 1b \n\t" : [ftmp0]"=&f"(ftmp[0]), [ftmp1]"=&f"(ftmp[1]), @@ -157,12 +149,10 @@ void ff_avg_pixels4_8_mmi(uint8_t *block, const uint8_t *pixels, ptrdiff_t line_size, int h) { double ftmp[4]; - mips_reg addr[3]; + mips_reg addr[2]; DECLARE_VAR_LOW32; - DECLARE_VAR_ADDRT; __asm__ volatile ( - PTR_ADDU "%[addr2], %[line_size], %[line_size] \n\t" "1: \n\t" PTR_ADDU "%[addr0], %[pixels], %[line_size] \n\t" MMI_ULWC1(%[ftmp0], %[pixels], 0x00) @@ -170,34 +160,21 @@ void ff_avg_pixels4_8_mmi(uint8_t *block, const uint8_t *pixels, PTR_ADDU "%[addr1], %[block], %[line_size] \n\t" MMI_ULWC1(%[ftmp2], %[block], 0x00) MMI_ULWC1(%[ftmp3], %[addr1], 0x00) - "pavgb %[ftmp0], %[ftmp0], %[ftmp2] \n\t" - "pavgb %[ftmp1], %[ftmp1], %[ftmp3] \n\t" - MMI_SWC1(%[ftmp0], %[block], 0x00) - MMI_SWXC1(%[ftmp1], %[block], %[line_size], 0x00) - PTR_ADDU "%[pixels], %[pixels], %[addr2] \n\t" - PTR_ADDU "%[block], %[block], %[addr2] \n\t" - PTR_ADDU "%[addr0], %[pixels], %[line_size] \n\t" - MMI_ULWC1(%[ftmp0], %[pixels], 0x00) - MMI_ULWC1(%[ftmp1], %[addr0], 0x00) - PTR_ADDU "%[addr1], %[block], %[line_size] \n\t" - MMI_ULWC1(%[ftmp2], %[block], 0x00) - MMI_ULWC1(%[ftmp3], %[addr1], 0x00) + PTR_ADDI "%[h], %[h], -0x02 \n\t" + "pavgb %[ftmp0], %[ftmp0], %[ftmp2] \n\t" "pavgb %[ftmp1], %[ftmp1], %[ftmp3] \n\t" MMI_SWC1(%[ftmp0], %[block], 0x00) - MMI_SWXC1(%[ftmp1], %[block], %[line_size], 0x00) - PTR_ADDU "%[pixels], %[pixels], %[addr2] \n\t" - PTR_ADDU "%[block], %[block], %[addr2] \n\t" + MMI_SWC1(%[ftmp1], %[addr1], 0x00) + PTR_ADDU "%[pixels], %[addr0], %[line_size] \n\t" + PTR_ADDU "%[block], %[addr1], %[line_size] \n\t" - PTR_ADDI "%[h], %[h], -0x04 \n\t" "bnez %[h], 1b \n\t" : [ftmp0]"=&f"(ftmp[0]), [ftmp1]"=&f"(ftmp[1]), [ftmp2]"=&f"(ftmp[2]), [ftmp3]"=&f"(ftmp[3]), RESTRICT_ASM_LOW32 - RESTRICT_ASM_ADDRT [addr0]"=&r"(addr[0]), [addr1]"=&r"(addr[1]), - [addr2]"=&r"(addr[2]), [block]"+&r"(block), [pixels]"+&r"(pixels), [h]"+&r"(h) : [line_size]"r"((mips_reg)line_size) @@ -330,50 +307,33 @@ inline void ff_put_pixels4_l2_8_mmi(uint8_t *dst, const uint8_t *src1, double ftmp[4]; mips_reg addr[5]; DECLARE_VAR_LOW32; - DECLARE_VAR_ADDRT; __asm__ volatile ( - PTR_ADDU "%[addr2], %[src_stride1], %[src_stride1] \n\t" - PTR_ADDU "%[addr3], %[src_stride2], %[src_stride2] \n\t" - PTR_ADDU "%[addr4], %[dst_stride], %[dst_stride] \n\t" "1: \n\t" PTR_ADDU "%[addr0], %[src1], %[src_stride1] \n\t" MMI_ULWC1(%[ftmp0], %[src1], 0x00) MMI_ULWC1(%[ftmp1], %[addr0], 0x00) - MMI_ULWC1(%[ftmp2], %[src2], 0x00) PTR_ADDU "%[addr1], %[src2], %[src_stride2] \n\t" - MMI_ULWC1(%[ftmp3], %[addr1], 0x00) - PTR_ADDU "%[src1], %[src1], %[addr2] \n\t" - "pavgb %[ftmp0], %[ftmp0], %[ftmp2] \n\t" - "pavgb %[ftmp1], %[ftmp1], %[ftmp3] \n\t" - MMI_SWC1(%[ftmp0], %[dst], 0x00) - MMI_SWXC1(%[ftmp1], %[dst], %[dst_stride], 0x00) - PTR_ADDU "%[src2], %[src2], %[addr3] \n\t" - PTR_ADDU "%[dst], %[dst], %[addr4] \n\t" - - PTR_ADDU "%[addr0], %[src1], %[src_stride1] \n\t" - MMI_ULWC1(%[ftmp0], %[src1], 0x00) - MMI_ULWC1(%[ftmp1], %[addr0], 0x00) MMI_ULWC1(%[ftmp2], %[src2], 0x00) - PTR_ADDU "%[addr1], %[src2], %[src_stride2] \n\t" MMI_ULWC1(%[ftmp3], %[addr1], 0x00) - PTR_ADDU "%[src1], %[src1], %[addr2] \n\t" + PTR_ADDU "%[src1], %[addr0], %[src_stride1] \n\t" + PTR_ADDU "%[src2], %[addr1], %[src_stride2] \n\t" + + PTR_ADDI "%[h], %[h], -0x02 \n\t" + "pavgb %[ftmp0], %[ftmp0], %[ftmp2] \n\t" "pavgb %[ftmp1], %[ftmp1], %[ftmp3] \n\t" MMI_SWC1(%[ftmp0], %[dst], 0x00) - MMI_SWXC1(%[ftmp1], %[dst], %[dst_stride], 0x00) - PTR_ADDU "%[src2], %[src2], %[addr3] \n\t" - PTR_ADDU "%[dst], %[dst], %[addr4] \n\t" + PTR_ADDU "%[dst], %[dst], %[dst_stride] \n\t" + MMI_SWC1(%[ftmp1], %[dst], 0x00) + PTR_ADDU "%[dst], %[dst], %[dst_stride] \n\t" - PTR_ADDI "%[h], %[h], -0x04 \n\t" "bnez %[h], 1b \n\t" : [ftmp0]"=&f"(ftmp[0]), [ftmp1]"=&f"(ftmp[1]), [ftmp2]"=&f"(ftmp[2]), [ftmp3]"=&f"(ftmp[3]), RESTRICT_ASM_LOW32 RESTRICT_ASM_ADDRT [addr0]"=&r"(addr[0]), [addr1]"=&r"(addr[1]), - [addr2]"=&r"(addr[2]), [addr3]"=&r"(addr[3]), - [addr4]"=&r"(addr[4]), [dst]"+&r"(dst), [src1]"+&r"(src1), [src2]"+&r"(src2), [h]"+&r"(h) : [dst_stride]"r"((mips_reg)dst_stride), @@ -530,62 +490,36 @@ inline void ff_avg_pixels4_l2_8_mmi(uint8_t *dst, const uint8_t *src1, double ftmp[6]; mips_reg addr[6]; DECLARE_VAR_LOW32; - DECLARE_VAR_ADDRT; __asm__ volatile ( - PTR_ADDU "%[addr2], %[src_stride1], %[src_stride1] \n\t" - PTR_ADDU "%[addr3], %[src_stride2], %[src_stride2] \n\t" - PTR_ADDU "%[addr4], %[dst_stride], %[dst_stride] \n\t" - "1: \n\t" PTR_ADDU "%[addr0], %[src1], %[src_stride1] \n\t" MMI_ULWC1(%[ftmp0], %[src1], 0x00) MMI_ULWC1(%[ftmp1], %[addr0], 0x00) - MMI_ULWC1(%[ftmp2], %[src2], 0x00) PTR_ADDU "%[addr1], %[src2], %[src_stride2] \n\t" - MMI_ULWC1(%[ftmp3], %[addr1], 0x00) - PTR_ADDU "%[src1], %[src1], %[addr2] \n\t" - "pavgb %[ftmp0], %[ftmp0], %[ftmp2] \n\t" - "pavgb %[ftmp1], %[ftmp1], %[ftmp3] \n\t" - PTR_ADDU "%[addr5], %[dst], %[dst_stride] \n\t" - MMI_ULWC1(%[ftmp4], %[dst], 0x00) - MMI_ULWC1(%[ftmp5], %[addr5], 0x00) - "pavgb %[ftmp0], %[ftmp0], %[ftmp4] \n\t" - "pavgb %[ftmp1], %[ftmp1], %[ftmp5] \n\t" - MMI_SWC1(%[ftmp0], %[dst], 0x00) - MMI_SWXC1(%[ftmp1], %[dst], %[dst_stride], 0x00) - PTR_ADDU "%[src2], %[src2], %[addr3] \n\t" - PTR_ADDU "%[dst], %[dst], %[addr4] \n\t" - - PTR_ADDU "%[addr0], %[src1], %[src_stride1] \n\t" - MMI_ULWC1(%[ftmp0], %[src1], 0x00) - MMI_ULWC1(%[ftmp1], %[addr0], 0x00) MMI_ULWC1(%[ftmp2], %[src2], 0x00) - PTR_ADDU "%[addr1], %[src2], %[src_stride2] \n\t" MMI_ULWC1(%[ftmp3], %[addr1], 0x00) - PTR_ADDU "%[src1], %[src1], %[addr2] \n\t" + PTR_ADDU "%[src1], %[addr0], %[src_stride1] \n\t" + PTR_ADDU "%[src2], %[addr1], %[src_stride2] \n\t" "pavgb %[ftmp0], %[ftmp0], %[ftmp2] \n\t" "pavgb %[ftmp1], %[ftmp1], %[ftmp3] \n\t" - PTR_ADDU "%[addr5], %[dst], %[dst_stride] \n\t" + PTR_ADDU "%[addr2], %[dst], %[dst_stride] \n\t" MMI_ULWC1(%[ftmp4], %[dst], 0x00) - MMI_ULWC1(%[ftmp5], %[addr5], 0x00) + MMI_ULWC1(%[ftmp5], %[addr2], 0x00) + PTR_ADDI "%[h], %[h], -0x02 \n\t" "pavgb %[ftmp0], %[ftmp0], %[ftmp4] \n\t" "pavgb %[ftmp1], %[ftmp1], %[ftmp5] \n\t" MMI_SWC1(%[ftmp0], %[dst], 0x00) - MMI_SWXC1(%[ftmp1], %[dst], %[dst_stride], 0x00) - PTR_ADDU "%[src2], %[src2], %[addr3] \n\t" - PTR_ADDU "%[dst], %[dst], %[addr4] \n\t" + MMI_SWC1(%[ftmp1], %[addr2], 0x00) + PTR_ADDU "%[dst], %[addr2], %[dst_stride] \n\t" - PTR_ADDI "%[h], %[h], -0x04 \n\t" "bnez %[h], 1b \n\t" : [ftmp0]"=&f"(ftmp[0]), [ftmp1]"=&f"(ftmp[1]), [ftmp2]"=&f"(ftmp[2]), [ftmp3]"=&f"(ftmp[3]), [ftmp4]"=&f"(ftmp[4]), [ftmp5]"=&f"(ftmp[5]), RESTRICT_ASM_LOW32 - RESTRICT_ASM_ADDRT [addr0]"=&r"(addr[0]), [addr1]"=&r"(addr[1]), - [addr2]"=&r"(addr[2]), [addr3]"=&r"(addr[3]), - [addr4]"=&r"(addr[4]), [addr5]"=&r"(addr[5]), + [addr2]"=&r"(addr[2]), [dst]"+&r"(dst), [src1]"+&r"(src1), [src2]"+&r"(src2), [h]"+&r"(h) : [dst_stride]"r"((mips_reg)dst_stride),