diff mbox

[FFmpeg-devel,v5] avutil/mips: Avoid instruction exception caused by gssqc1/gslqc1.

Message ID 1564536601-21800-1-git-send-email-yinshiyou-hf@loongson.cn
State Accepted
Commit 11f99a9a45925e14409eff65606973676d7376b6
Headers show

Commit Message

殷时友 July 31, 2019, 1:30 a.m. UTC
Ensure the address accesed by gssqc1/gslqc1 are 16-byte aligned.
---
 libavcodec/mips/simple_idct_mmi.c | 2 +-
 libavutil/mips/mmiutils.h         | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

Comments

Reimar Döffinger July 31, 2019, 6:33 a.m. UTC | #1
Looks good to me

On 31.07.2019, at 03:30, Shiyou Yin <yinshiyou-hf@loongson.cn> wrote:

> Ensure the address accesed by gssqc1/gslqc1 are 16-byte aligned.
> ---
> libavcodec/mips/simple_idct_mmi.c | 2 +-
> libavutil/mips/mmiutils.h         | 2 +-
> 2 files changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/libavcodec/mips/simple_idct_mmi.c b/libavcodec/mips/simple_idct_mmi.c
> index 7f4bb74..73d797f 100644
> --- a/libavcodec/mips/simple_idct_mmi.c
> +++ b/libavcodec/mips/simple_idct_mmi.c
> @@ -39,7 +39,7 @@
> #define COL_SHIFT 20
> #define DC_SHIFT 3
> 
> -DECLARE_ALIGNED(8, const int16_t, W_arr)[46] = {
> +DECLARE_ALIGNED(16, const int16_t, W_arr)[46] = {
>     W4,  W2,  W4,  W6,
>     W1,  W3,  W5,  W7,
>     W4,  W6, -W4, -W2,
> diff --git a/libavutil/mips/mmiutils.h b/libavutil/mips/mmiutils.h
> index 05f6b31..8f692e8 100644
> --- a/libavutil/mips/mmiutils.h
> +++ b/libavutil/mips/mmiutils.h
> @@ -205,7 +205,7 @@
>  * backup register
>  */
> #define BACKUP_REG \
> -  double temp_backup_reg[8];                                    \
> +  LOCAL_ALIGNED_16(double, temp_backup_reg, [8]);               \
>   if (_MIPS_SIM == _ABI64)                                      \
>     __asm__ volatile (                                          \
>       "gssqc1       $f25,      $f24,       0x00(%[temp])  \n\t" \
> -- 
> 2.1.0
> 
> 
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Reimar Döffinger Aug. 2, 2019, 5:03 p.m. UTC | #2
On Wed, Jul 31, 2019 at 09:30:01AM +0800, Shiyou Yin wrote:
> Ensure the address accesed by gssqc1/gslqc1 are 16-byte aligned.

Pushed, thanks.
diff mbox

Patch

diff --git a/libavcodec/mips/simple_idct_mmi.c b/libavcodec/mips/simple_idct_mmi.c
index 7f4bb74..73d797f 100644
--- a/libavcodec/mips/simple_idct_mmi.c
+++ b/libavcodec/mips/simple_idct_mmi.c
@@ -39,7 +39,7 @@ 
 #define COL_SHIFT 20
 #define DC_SHIFT 3
 
-DECLARE_ALIGNED(8, const int16_t, W_arr)[46] = {
+DECLARE_ALIGNED(16, const int16_t, W_arr)[46] = {
     W4,  W2,  W4,  W6,
     W1,  W3,  W5,  W7,
     W4,  W6, -W4, -W2,
diff --git a/libavutil/mips/mmiutils.h b/libavutil/mips/mmiutils.h
index 05f6b31..8f692e8 100644
--- a/libavutil/mips/mmiutils.h
+++ b/libavutil/mips/mmiutils.h
@@ -205,7 +205,7 @@ 
  * backup register
  */
 #define BACKUP_REG \
-  double temp_backup_reg[8];                                    \
+  LOCAL_ALIGNED_16(double, temp_backup_reg, [8]);               \
   if (_MIPS_SIM == _ABI64)                                      \
     __asm__ volatile (                                          \
       "gssqc1       $f25,      $f24,       0x00(%[temp])  \n\t" \