From patchwork Tue Jun 2 14:15:05 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiaxun Yang X-Patchwork-Id: 20072 Return-Path: X-Original-To: patchwork@ffaux-bg.ffmpeg.org Delivered-To: patchwork@ffaux-bg.ffmpeg.org Received: from ffbox0-bg.mplayerhq.hu (ffbox0-bg.ffmpeg.org [79.124.17.100]) by ffaux.localdomain (Postfix) with ESMTP id D575E44A526 for ; Tue, 2 Jun 2020 17:16:48 +0300 (EEST) Received: from [127.0.1.1] (localhost [127.0.0.1]) by ffbox0-bg.mplayerhq.hu (Postfix) with ESMTP id BDC6568AE72; Tue, 2 Jun 2020 17:16:48 +0300 (EEST) X-Original-To: ffmpeg-devel@ffmpeg.org Delivered-To: ffmpeg-devel@ffmpeg.org Received: from sender2-op-o12.zoho.com.cn (sender2-op-o12.zoho.com.cn [163.53.93.243]) by ffbox0-bg.mplayerhq.hu (Postfix) with ESMTPS id 73707680180 for ; Tue, 2 Jun 2020 17:16:39 +0300 (EEST) ARC-Seal: i=1; a=rsa-sha256; t=1591107389; cv=none; d=zoho.com.cn; s=zohoarc; b=TSSry6QKnBo0e5thD0qglWFs997JHTbEGjx+falUP8TXp+2QY7fqJSn+QYuVUaUa8DcOWqNCoNhv3npa0++/CIbR46IePcPLAGoLDG5LD5mF3NRdd8E/LRX/axfzeBXcYhJrnNfjSWsZbpbWSLYbKsJNwLvWs6DXJ6L1IOUgXZI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com.cn; s=zohoarc; t=1591107389; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Subject:To; bh=emtOShO4X8s8ULQwg7s/0hORuQ0gOt8x0UC0xKdB3iE=; b=VNoZJ8B7jfdBwgSzWlP+y/VI5vPxrxGrbJyLxMf7x566RUiw50CErzehabYeTWtxDEw9DYET9ueF1RAXVjDU5BXnKvY4S5RPT5iRqq2FXDqzuOSxIebneT4Y5LolTmaKp5dVPqVHwzJ/NPdyElt9Hw54knYofPyK4/AiKNHSGC8= ARC-Authentication-Results: i=1; mx.zoho.com.cn; dkim=pass header.i=flygoat.com; spf=pass smtp.mailfrom=jiaxun.yang@flygoat.com; dmarc=pass header.from= header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1591107389; s=mail; d=flygoat.com; i=jiaxun.yang@flygoat.com; h=From:To:Cc:Message-ID:Subject:Date:In-Reply-To:References:MIME-Version:Content-Transfer-Encoding:Content-Type; bh=emtOShO4X8s8ULQwg7s/0hORuQ0gOt8x0UC0xKdB3iE=; b=eXybcNDtPlfl4yn4Kka2fY9uehctSWylT80Cm2HaNpAHeUhBvcBP1ilMcdPiGvhG TYo43MP7TXqBmvCfxem3CkZtjVJ4xFMLHaNYXaHPBfmp9H2zNfjJFcLdXKdZ7pr657h 738ABvtsZ0N8J8UUPsEoc3PhEzMYAK5sXduEL1ZQ= Received: from halation.net.flygoat.com (60.177.188.90 [60.177.188.90]) by mx.zoho.com.cn with SMTPS id 159110738683110.073454320114479; Tue, 2 Jun 2020 22:16:26 +0800 (CST) From: Jiaxun Yang To: ffmpeg-devel@ffmpeg.org Message-ID: <20200602141507.11151-3-jiaxun.yang@flygoat.com> Date: Tue, 2 Jun 2020 22:15:05 +0800 X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200602141507.11151-1-jiaxun.yang@flygoat.com> References: <20200602141507.11151-1-jiaxun.yang@flygoat.com> MIME-Version: 1.0 X-ZohoCNMailClient: External Subject: [FFmpeg-devel] [PATCH v2 2/4] libavutils: Add parse_r helper for MIPS X-BeenThere: ffmpeg-devel@ffmpeg.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: FFmpeg development discussions and patches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: FFmpeg development discussions and patches Cc: yinshiyou@loongson.cn, Jiaxun Yang Errors-To: ffmpeg-devel-bounces@ffmpeg.org Sender: "ffmpeg-devel" That helper grab from kernel code can allow us to inline newer instructions (not implemented by the assembler) in a elegant manner. Signed-off-by: Jiaxun Yang --- libavutil/mips/asmdefs.h | 42 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/libavutil/mips/asmdefs.h b/libavutil/mips/asmdefs.h index 748119918a..7e0e4cf575 100644 --- a/libavutil/mips/asmdefs.h +++ b/libavutil/mips/asmdefs.h @@ -55,4 +55,46 @@ # define PTR_SLL "sll " #endif +/* + * parse_r var, r - Helper assembler macro for parsing register names. + * + * This converts the register name in $n form provided in \r to the + * corresponding register number, which is assigned to the variable \var. It is + * needed to allow explicit encoding of instructions in inline assembly where + * registers are chosen by the compiler in $n form, allowing us to avoid using + * fixed register numbers. + * + * It also allows newer instructions (not implemented by the assembler) to be + * transparently implemented using assembler macros, instead of needing separate + * cases depending on toolchain support. + * + * Simple usage example: + * __asm__ __volatile__("parse_r __rt, %0\n\t" + * ".insn\n\t" + * "# di %0\n\t" + * ".word (0x41606000 | (__rt << 16))" + * : "=r" (status); + */ + +/* Match an individual register number and assign to \var */ +#define _IFC_REG(n) \ + ".ifc \\r, $" #n "\n\t" \ + "\\var = " #n "\n\t" \ + ".endif\n\t" + +__asm__(".macro parse_r var r\n\t" + "\\var = -1\n\t" + _IFC_REG(0) _IFC_REG(1) _IFC_REG(2) _IFC_REG(3) + _IFC_REG(4) _IFC_REG(5) _IFC_REG(6) _IFC_REG(7) + _IFC_REG(8) _IFC_REG(9) _IFC_REG(10) _IFC_REG(11) + _IFC_REG(12) _IFC_REG(13) _IFC_REG(14) _IFC_REG(15) + _IFC_REG(16) _IFC_REG(17) _IFC_REG(18) _IFC_REG(19) + _IFC_REG(20) _IFC_REG(21) _IFC_REG(22) _IFC_REG(23) + _IFC_REG(24) _IFC_REG(25) _IFC_REG(26) _IFC_REG(27) + _IFC_REG(28) _IFC_REG(29) _IFC_REG(30) _IFC_REG(31) + ".iflt \\var\n\t" + ".error \"Unable to parse register name \\r\"\n\t" + ".endif\n\t" + ".endm"); + #endif /* AVCODEC_MIPS_ASMDEFS_H */