From patchwork Fri Feb 19 05:28:32 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiaxun Yang X-Patchwork-Id: 25778 Return-Path: X-Original-To: patchwork@ffaux-bg.ffmpeg.org Delivered-To: patchwork@ffaux-bg.ffmpeg.org Received: from ffbox0-bg.mplayerhq.hu (ffbox0-bg.ffmpeg.org [79.124.17.100]) by ffaux.localdomain (Postfix) with ESMTP id 0D83A44ADFD for ; Fri, 19 Feb 2021 07:29:05 +0200 (EET) Received: from [127.0.1.1] (localhost [127.0.0.1]) by ffbox0-bg.mplayerhq.hu (Postfix) with ESMTP id E65E868A17B; Fri, 19 Feb 2021 07:29:04 +0200 (EET) X-Original-To: ffmpeg-devel@ffmpeg.org Delivered-To: ffmpeg-devel@ffmpeg.org Received: from out2-smtp.messagingengine.com (out2-smtp.messagingengine.com [66.111.4.26]) by ffbox0-bg.mplayerhq.hu (Postfix) with ESMTPS id E6B65680534 for ; Fri, 19 Feb 2021 07:28:58 +0200 (EET) Received: from compute6.internal (compute6.nyi.internal [10.202.2.46]) by mailout.nyi.internal (Postfix) with ESMTP id 00E285C0129; Fri, 19 Feb 2021 00:28:58 -0500 (EST) Received: from mailfrontend2 ([10.202.2.163]) by compute6.internal (MEProxy); Fri, 19 Feb 2021 00:28:58 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=flygoat.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; s=fm1; bh=lyLBFKJSsiUDV jV10UTWKoiXdECTNkmamf0PZ1G2TxY=; b=p81OIMGwo8j0dKG5E6KxibcSZB/hI Arwy4O57A+4NJjkH83DE0tWIK6mJYc2U6sMztZNXSBRlfXggJHKDOYvUQ4dZVkka CtCLxZm6/DJlukGccf4CBM4A6bvAUrqXWp0UJ9HctQeuXL+8JYvBqoaGtjETihIU HEVFJu3oA6T34VvsluDuGiDm/Uki07B3PPplK5u0qkM7u3VO7mu+s7kTXb6QyQlr bJDMLjLtu1JVyNJREe0QADNLUjcgbijpeqDSDpzV35B7uiumvUOv/mMeUvKneoSX ThYjLeTK2t9YKSkph7qw57lVMJXTQ45O+l7FVw07BLbau1faLqKjxL5rg== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:content-transfer-encoding:date:from :in-reply-to:message-id:mime-version:references:subject:to :x-me-proxy:x-me-proxy:x-me-sender:x-me-sender:x-sasl-enc; s= fm2; bh=lyLBFKJSsiUDVjV10UTWKoiXdECTNkmamf0PZ1G2TxY=; b=fqD48/Wm 5GvUYNvHW7cMONZ2afisUdKL2OkWU0EjxlFIgz1cHZb3lKfDS9TvGbu4GButtFzr VtaXTg64XsMnn/YCd7WAbF+WI1KuLMphHT4SqTl9PeRnfxQZgUYEhKm0oaBYf6jX fT/lKIpNofonI1AC9CQeNp9xFjWKMjgHc1Clae8k0BXYQFldokJjPquhiFW5ufNR 3oCx4jFz3RCcV7qu0RUIPgVBn/LiXBActKs2QuGJEp9xexuApINvCujIMA4zni7s owI+5UYAqsMULKwb6PVMLQw3EIB4kyeaW7SYNxpPBugkSaikp/brOslbQ8z+/f5C XWS23P43LM7xMA== X-ME-Sender: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgeduledrjeehgdekvdcutefuodetggdotefrodftvf curfhrohhfihhlvgemucfhrghsthforghilhdpqfgfvfdpuffrtefokffrpgfnqfghnecu uegrihhlohhuthemuceftddtnecunecujfgurhephffvufffkffojghfggfgsedtkeertd ertddtnecuhfhrohhmpeflihgrgihunhcujggrnhhguceojhhirgiguhhnrdihrghnghes fhhlhihgohgrthdrtghomheqnecuggftrfgrthhtvghrnhepjeeihffgteelkeelffduke dtheevudejvdegkeekjeefhffhhfetudetgfdtffeunecukfhppedukeefrdduheejrdef ledrudeiudenucevlhhushhtvghrufhiiigvpedtnecurfgrrhgrmhepmhgrihhlfhhroh hmpehjihgrgihunhdrhigrnhhgsehflhihghhorghtrdgtohhm X-ME-Proxy: Received: from strike.202.net.flygoat.com (unknown [183.157.39.161]) by mail.messagingengine.com (Postfix) with ESMTPA id 645B91080057; Fri, 19 Feb 2021 00:28:54 -0500 (EST) From: Jiaxun Yang To: ffmpeg-devel@ffmpeg.org Date: Fri, 19 Feb 2021 13:28:32 +0800 Message-Id: <20210219052834.533558-3-jiaxun.yang@flygoat.com> X-Mailer: git-send-email 2.30.1 In-Reply-To: <20210219052834.533558-1-jiaxun.yang@flygoat.com> References: <20210219052834.533558-1-jiaxun.yang@flygoat.com> MIME-Version: 1.0 Subject: [FFmpeg-devel] [PATCH 2/4] avutil/mips: Extract load store with shift C1 pair marco X-BeenThere: ffmpeg-devel@ffmpeg.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: FFmpeg development discussions and patches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: FFmpeg development discussions and patches Cc: yinshiyou-hf@loongson.cn, guxiwei-hf@loongson.cn, Jiaxun Yang Errors-To: ffmpeg-devel-bounces@ffmpeg.org Sender: "ffmpeg-devel" We're doing some fancy hacks with load store with shift C1 beside unaligned load store. Create a marco for l/r pair to allow us use it in these places. Signed-off-by: Jiaxun Yang --- libavutil/mips/mmiutils.h | 49 ++++++++++++++++++++++++--------------- 1 file changed, 30 insertions(+), 19 deletions(-) diff --git a/libavutil/mips/mmiutils.h b/libavutil/mips/mmiutils.h index fb85a4dd1b..3994085057 100644 --- a/libavutil/mips/mmiutils.h +++ b/libavutil/mips/mmiutils.h @@ -55,8 +55,9 @@ #define MMI_LWC1(fp, addr, bias) \ "lwc1 "#fp", "#bias"("#addr") \n\t" -#define MMI_ULWC1(fp, addr, bias) \ - "ulw %[low32], "#bias"("#addr") \n\t" \ +#define MMI_LWLRC1(fp, addr, bias, off) \ + "lwl %[low32], "#bias"+"#off"("#addr") \n\t" \ + "lwr %[low32], "#bias"("#addr") \n\t" \ "mtc1 %[low32], "#fp" \n\t" #define MMI_LWXC1(fp, addr, stride, bias) \ @@ -66,9 +67,10 @@ #define MMI_SWC1(fp, addr, bias) \ "swc1 "#fp", "#bias"("#addr") \n\t" -#define MMI_USWC1(fp, addr, bias) \ +#define MMI_SWLRC1(fp, addr, bias, off) \ "mfc1 %[low32], "#fp" \n\t" \ - "usw %[low32], "#bias"("#addr") \n\t" + "swl %[low32], "#bias"+"#off"("#addr") \n\t" \ + "swr %[low32], "#bias"("#addr") \n\t" #define MMI_SWXC1(fp, addr, stride, bias) \ PTR_ADDU "%[addrt], "#addr", "#stride" \n\t" \ @@ -77,8 +79,9 @@ #define MMI_LDC1(fp, addr, bias) \ "ldc1 "#fp", "#bias"("#addr") \n\t" -#define MMI_ULDC1(fp, addr, bias) \ - "uld %[all64], "#bias"("#addr") \n\t" \ +#define MMI_LDLRC1(fp, addr, bias, off) \ + "ldl %[all64], "#bias"+"#off"("#addr") \n\t" \ + "ldr %[all64], "#bias"("#addr") \n\t" \ "dmtc1 %[all64], "#fp" \n\t" #define MMI_LDXC1(fp, addr, stride, bias) \ @@ -88,9 +91,10 @@ #define MMI_SDC1(fp, addr, bias) \ "sdc1 "#fp", "#bias"("#addr") \n\t" -#define MMI_USDC1(fp, addr, bias) \ +#define MMI_SDLRC1(fp, addr, bias, off) \ "dmfc1 %[all64], "#fp" \n\t" \ - "usd %[all64], "#bias"("#addr") \n\t" + "sdl %[all64], "#bias"+"#off"("#addr") \n\t" \ + "sdr %[all64], "#bias"("#addr") \n\t" #define MMI_SDXC1(fp, addr, stride, bias) \ PTR_ADDU "%[addrt], "#addr", "#stride" \n\t" \ @@ -139,17 +143,18 @@ #define DECLARE_VAR_LOW32 int32_t low32 #define RESTRICT_ASM_LOW32 [low32]"=&r"(low32), -#define MMI_ULWC1(fp, addr, bias) \ - "ulw %[low32], "#bias"("#addr") \n\t" \ - "mtc1 %[low32], "#fp" \n\t" +#define MMI_LWLRC1(fp, addr, bias, off) \ + "lwl %[low32], "#bias"+"#off"("#addr") \n\t" \ + "lwr %[low32], "#bias"("#addr") \n\t" \ + "mtc1 %[low32], "#fp" \n\t" #else /* _MIPS_SIM != _ABIO32 */ #define DECLARE_VAR_LOW32 #define RESTRICT_ASM_LOW32 -#define MMI_ULWC1(fp, addr, bias) \ - "gslwlc1 "#fp", 3+"#bias"("#addr") \n\t" \ +#define MMI_LWLRC1(fp, addr, bias, off) \ + "gslwlc1 "#fp", "#off"+"#bias"("#addr") \n\t" \ "gslwrc1 "#fp", "#bias"("#addr") \n\t" #endif /* _MIPS_SIM != _ABIO32 */ @@ -160,8 +165,8 @@ #define MMI_SWC1(fp, addr, bias) \ "swc1 "#fp", "#bias"("#addr") \n\t" -#define MMI_USWC1(fp, addr, bias) \ - "gsswlc1 "#fp", 3+"#bias"("#addr") \n\t" \ +#define MMI_SWLRC1(fp, addr, bias, off) \ + "gsswlc1 "#fp", "#off"+"#bias"("#addr") \n\t" \ "gsswrc1 "#fp", "#bias"("#addr") \n\t" #define MMI_SWXC1(fp, addr, stride, bias) \ @@ -170,8 +175,8 @@ #define MMI_LDC1(fp, addr, bias) \ "ldc1 "#fp", "#bias"("#addr") \n\t" -#define MMI_ULDC1(fp, addr, bias) \ - "gsldlc1 "#fp", 7+"#bias"("#addr") \n\t" \ +#define MMI_LDLRC1(fp, addr, bias, off) \ + "gsldlc1 "#fp", "#off"+"#bias"("#addr") \n\t" \ "gsldrc1 "#fp", "#bias"("#addr") \n\t" #define MMI_LDXC1(fp, addr, stride, bias) \ @@ -180,8 +185,8 @@ #define MMI_SDC1(fp, addr, bias) \ "sdc1 "#fp", "#bias"("#addr") \n\t" -#define MMI_USDC1(fp, addr, bias) \ - "gssdlc1 "#fp", 7+"#bias"("#addr") \n\t" \ +#define MMI_SDLRC1(fp, addr, bias, off) \ + "gssdlc1 "#fp", "#off"+"#bias"("#addr") \n\t" \ "gssdrc1 "#fp", "#bias"("#addr") \n\t" #define MMI_SDXC1(fp, addr, stride, bias) \ @@ -201,6 +206,12 @@ #endif /* HAVE_LOONGSON2 */ +#define MMI_ULWC1(fp, addr, bias) MMI_LWLRC1(fp, addr, bias, 3) +#define MMI_USWC1(fp, addr, bias) MMI_SWLRC1(fp, addr, bias, 3) + +#define MMI_ULDC1(fp, addr, bias) MMI_LDLRC1(fp, addr, bias, 7) +#define MMI_USDC1(fp, addr, bias) MMI_SDLRC1(fp, addr, bias, 7) + /** * Backup saved registers * We're not using compiler's clobber list as it's not smart enough