From patchwork Fri Feb 19 05:28:34 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiaxun Yang X-Patchwork-Id: 25780 Return-Path: X-Original-To: patchwork@ffaux-bg.ffmpeg.org Delivered-To: patchwork@ffaux-bg.ffmpeg.org Received: from ffbox0-bg.mplayerhq.hu (ffbox0-bg.ffmpeg.org [79.124.17.100]) by ffaux.localdomain (Postfix) with ESMTP id 291F544ADFD for ; Fri, 19 Feb 2021 07:29:12 +0200 (EET) Received: from [127.0.1.1] (localhost [127.0.0.1]) by ffbox0-bg.mplayerhq.hu (Postfix) with ESMTP id 0EE78680534; Fri, 19 Feb 2021 07:29:12 +0200 (EET) X-Original-To: ffmpeg-devel@ffmpeg.org Delivered-To: ffmpeg-devel@ffmpeg.org Received: from out2-smtp.messagingengine.com (out2-smtp.messagingengine.com [66.111.4.26]) by ffbox0-bg.mplayerhq.hu (Postfix) with ESMTPS id 27EA9680534 for ; Fri, 19 Feb 2021 07:29:06 +0200 (EET) Received: from compute6.internal (compute6.nyi.internal [10.202.2.46]) by mailout.nyi.internal (Postfix) with ESMTP id 33E0D5C011C; Fri, 19 Feb 2021 00:29:05 -0500 (EST) Received: from mailfrontend2 ([10.202.2.163]) by compute6.internal (MEProxy); Fri, 19 Feb 2021 00:29:05 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=flygoat.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; s=fm1; bh=hBUPjOdcm+y1o B1G37fQEeHfNyvu8R+KyrVB41Tw3d4=; b=ezoGGJ21OfHkDOL6MganHX0gMUdf/ U5KqXjjvEA/CQqXB7I4zjVrvoBEpmHDbgU5iGd2pk4pLQtrg+Y+dwkMYd8fx6WwR Ht+2x/O4K4jae8BzxUTu6yjeM0cuTGOPVs3coL/Cs6kQG0T6wwLzFNmn87Rux2rM uJWvpfGYghYFy6rxm4lSrDnXnfF/iP+G3eQPe2p69+OLLpFVLx2WSAiqscFT9vfW q5hk0S4PUnQiR+N6DXjQKysG92lDHt1R6XaiI6PwFeobgqUFOIgN2GdTS7Hprn/d +fxpZ60nuuJjZrM1JNV9/25veModC6e7/k5ms5mWP1rxV/xD03Vl351Kw== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:content-transfer-encoding:date:from :in-reply-to:message-id:mime-version:references:subject:to :x-me-proxy:x-me-proxy:x-me-sender:x-me-sender:x-sasl-enc; s= fm2; bh=hBUPjOdcm+y1oB1G37fQEeHfNyvu8R+KyrVB41Tw3d4=; b=BesLM+wA aRXG5gIla4ZUhQFf0ceLJnmzv71vFs5Cz7YbGW4nxpCjr1txVtImqb2TA2N4LSH6 TqKbUqTugrkLkKemUDXf8S6qznx26MvVOqzFe8YRb/bhtkdrhCcckLvF/LvFeH2o 7LiE51GLIeBxTLjEXWhACygNID4osbqiiCXAHAnCViXiuzNknBopwmUuBx1n6uHI V+TYhJuhaaCC8evRn0IxuFS/YPT3btx8s/uNXNqI+n6eaECNxpl2ReX9jcr7FUyt 3gF7jwagAnnHuL4c8ECFw1yeABxid9cXFQd2GrkY5MIQF4vND/rR5T3VElIoQIY1 1jO0vhgQsI1tlQ== X-ME-Sender: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgeduledrjeehgdekvdcutefuodetggdotefrodftvf curfhrohhfihhlvgemucfhrghsthforghilhdpqfgfvfdpuffrtefokffrpgfnqfghnecu uegrihhlohhuthemuceftddtnecunecujfgurhephffvufffkffojghfggfgsedtkeertd ertddtnecuhfhrohhmpeflihgrgihunhcujggrnhhguceojhhirgiguhhnrdihrghnghes fhhlhihgohgrthdrtghomheqnecuggftrfgrthhtvghrnhepjeeihffgteelkeelffduke dtheevudejvdegkeekjeefhffhhfetudetgfdtffeunecukfhppedukeefrdduheejrdef ledrudeiudenucevlhhushhtvghrufhiiigvpedvnecurfgrrhgrmhepmhgrihhlfhhroh hmpehjihgrgihunhdrhigrnhhgsehflhihghhorghtrdgtohhm X-ME-Proxy: Received: from strike.202.net.flygoat.com (unknown [183.157.39.161]) by mail.messagingengine.com (Postfix) with ESMTPA id 2F9D31080057; Fri, 19 Feb 2021 00:29:02 -0500 (EST) From: Jiaxun Yang To: ffmpeg-devel@ffmpeg.org Date: Fri, 19 Feb 2021 13:28:34 +0800 Message-Id: <20210219052834.533558-5-jiaxun.yang@flygoat.com> X-Mailer: git-send-email 2.30.1 In-Reply-To: <20210219052834.533558-1-jiaxun.yang@flygoat.com> References: <20210219052834.533558-1-jiaxun.yang@flygoat.com> MIME-Version: 1.0 Subject: [FFmpeg-devel] [PATCH 4/4] avutil/mips: Use $at as MMI macro temporary register X-BeenThere: ffmpeg-devel@ffmpeg.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: FFmpeg development discussions and patches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: FFmpeg development discussions and patches Cc: yinshiyou-hf@loongson.cn, guxiwei-hf@loongson.cn, Jiaxun Yang Errors-To: ffmpeg-devel-bounces@ffmpeg.org Sender: "ffmpeg-devel" Some function had exceed 30 inline assembly register oprands limiation when using LOONGSON2 version of MMI macros. We can avoid that by take $at, which is register reserved for assembler, as temporary register. As none of instructions used in these macros is pseudo, it is safe to utilize $at here. Signed-off-by: Jiaxun Yang --- libavutil/mips/mmiutils.h | 115 +++++++++++++++++++++++--------------- 1 file changed, 69 insertions(+), 46 deletions(-) diff --git a/libavutil/mips/mmiutils.h b/libavutil/mips/mmiutils.h index 3994085057..7b7b405ddf 100644 --- a/libavutil/mips/mmiutils.h +++ b/libavutil/mips/mmiutils.h @@ -27,78 +27,107 @@ #include "config.h" #include "libavutil/mips/asmdefs.h" -#if HAVE_LOONGSON2 +/* + * These were used to define temporary registers for MMI marcos + * however now we're using $at. They're theoretically unnecessary + * but just leave them here to avoid mess. + */ +#define DECLARE_VAR_LOW32 +#define RESTRICT_ASM_LOW32 +#define DECLARE_VAR_ALL64 +#define RESTRICT_ASM_ALL64 +#define DECLARE_VAR_ADDRT +#define RESTRICT_ASM_ADDRT -#define DECLARE_VAR_LOW32 int32_t low32 -#define RESTRICT_ASM_LOW32 [low32]"=&r"(low32), -#define DECLARE_VAR_ALL64 int64_t all64 -#define RESTRICT_ASM_ALL64 [all64]"=&r"(all64), -#define DECLARE_VAR_ADDRT mips_reg addrt -#define RESTRICT_ASM_ADDRT [addrt]"=&r"(addrt), +#if HAVE_LOONGSON2 #define MMI_LWX(reg, addr, stride, bias) \ - PTR_ADDU "%[addrt], "#addr", "#stride" \n\t" \ - "lw "#reg", "#bias"(%[addrt]) \n\t" + ".set noat \n\t" \ + PTR_ADDU "$at, "#addr", "#stride" \n\t" \ + "lw "#reg", "#bias"($at) \n\t" \ + ".set at \n\t" #define MMI_SWX(reg, addr, stride, bias) \ - PTR_ADDU "%[addrt], "#addr", "#stride" \n\t" \ - "sw "#reg", "#bias"(%[addrt]) \n\t" + ".set noat \n\t" \ + PTR_ADDU "$at, "#addr", "#stride" \n\t" \ + "sw "#reg", "#bias"($at) \n\t" \ + ".set at \n\t" #define MMI_LDX(reg, addr, stride, bias) \ - PTR_ADDU "%[addrt], "#addr", "#stride" \n\t" \ - "ld "#reg", "#bias"(%[addrt]) \n\t" + ".set noat \n\t" \ + PTR_ADDU "$at, "#addr", "#stride" \n\t" \ + "ld "#reg", "#bias"($at) \n\t" \ + ".set at \n\t" #define MMI_SDX(reg, addr, stride, bias) \ - PTR_ADDU "%[addrt], "#addr", "#stride" \n\t" \ - "sd "#reg", "#bias"(%[addrt]) \n\t" + ".set noat \n\t" \ + PTR_ADDU "$at, "#addr", "#stride" \n\t" \ + "sd "#reg", "#bias"($at) \n\t" \ + ".set at \n\t" #define MMI_LWC1(fp, addr, bias) \ "lwc1 "#fp", "#bias"("#addr") \n\t" #define MMI_LWLRC1(fp, addr, bias, off) \ - "lwl %[low32], "#bias"+"#off"("#addr") \n\t" \ - "lwr %[low32], "#bias"("#addr") \n\t" \ - "mtc1 %[low32], "#fp" \n\t" + ".set noat \n\t" \ + "lwl $at, "#bias"+"#off"("#addr") \n\t" \ + "lwr $at, "#bias"("#addr") \n\t" \ + "mtc1 $at, "#fp" \n\t" \ + ".set at \n\t" #define MMI_LWXC1(fp, addr, stride, bias) \ - PTR_ADDU "%[addrt], "#addr", "#stride" \n\t" \ - MMI_LWC1(fp, %[addrt], bias) + ".set noat \n\t" \ + PTR_ADDU "$at, "#addr", "#stride" \n\t" \ + MMI_LWC1(fp, $at, bias) \ + ".set at \n\t" #define MMI_SWC1(fp, addr, bias) \ "swc1 "#fp", "#bias"("#addr") \n\t" #define MMI_SWLRC1(fp, addr, bias, off) \ - "mfc1 %[low32], "#fp" \n\t" \ - "swl %[low32], "#bias"+"#off"("#addr") \n\t" \ - "swr %[low32], "#bias"("#addr") \n\t" + ".set noat \n\t" \ + "mfc1 $at, "#fp" \n\t" \ + "swl $at, "#bias"+"#off"("#addr") \n\t" \ + "swr $at, "#bias"("#addr") \n\t" \ + ".set at \n\t" #define MMI_SWXC1(fp, addr, stride, bias) \ - PTR_ADDU "%[addrt], "#addr", "#stride" \n\t" \ - MMI_SWC1(fp, %[addrt], bias) + ".set noat \n\t" \ + PTR_ADDU "$at, "#addr", "#stride" \n\t" \ + MMI_SWC1(fp, $at, bias) \ + ".set at \n\t" #define MMI_LDC1(fp, addr, bias) \ "ldc1 "#fp", "#bias"("#addr") \n\t" #define MMI_LDLRC1(fp, addr, bias, off) \ - "ldl %[all64], "#bias"+"#off"("#addr") \n\t" \ - "ldr %[all64], "#bias"("#addr") \n\t" \ - "dmtc1 %[all64], "#fp" \n\t" + ".set noat \n\t" \ + "ldl $at, "#bias"+"#off"("#addr") \n\t" \ + "ldr $at, "#bias"("#addr") \n\t" \ + "dmtc1 $at, "#fp" \n\t" \ + ".set at \n\t" #define MMI_LDXC1(fp, addr, stride, bias) \ - PTR_ADDU "%[addrt], "#addr", "#stride" \n\t" \ - MMI_LDC1(fp, %[addrt], bias) + ".set noat \n\t" \ + PTR_ADDU "$at, "#addr", "#stride" \n\t" \ + MMI_LDC1(fp, $at, bias) \ + ".set at \n\t" #define MMI_SDC1(fp, addr, bias) \ "sdc1 "#fp", "#bias"("#addr") \n\t" #define MMI_SDLRC1(fp, addr, bias, off) \ - "dmfc1 %[all64], "#fp" \n\t" \ - "sdl %[all64], "#bias"+"#off"("#addr") \n\t" \ - "sdr %[all64], "#bias"("#addr") \n\t" + ".set noat \n\t" \ + "dmfc1 $at, "#fp" \n\t" \ + "sdl $at, "#bias"+"#off"("#addr") \n\t" \ + "sdr $at, "#bias"("#addr") \n\t" \ + ".set at \n\t" #define MMI_SDXC1(fp, addr, stride, bias) \ - PTR_ADDU "%[addrt], "#addr", "#stride" \n\t" \ - MMI_SDC1(fp, %[addrt], bias) + ".set noat \n\t" \ + PTR_ADDU "$at, "#addr", "#stride" \n\t" \ + MMI_SDC1(fp, $at, bias) \ + ".set at \n\t" #define MMI_LQ(reg1, reg2, addr, bias) \ "ld "#reg1", "#bias"("#addr") \n\t" \ @@ -118,11 +147,6 @@ #elif HAVE_LOONGSON3 /* !HAVE_LOONGSON2 */ -#define DECLARE_VAR_ALL64 -#define RESTRICT_ASM_ALL64 -#define DECLARE_VAR_ADDRT -#define RESTRICT_ASM_ADDRT - #define MMI_LWX(reg, addr, stride, bias) \ "gslwx "#reg", "#bias"("#addr", "#stride") \n\t" @@ -140,13 +164,12 @@ #if _MIPS_SIM == _ABIO32 /* workaround for 3A2000 gslwlc1 bug */ -#define DECLARE_VAR_LOW32 int32_t low32 -#define RESTRICT_ASM_LOW32 [low32]"=&r"(low32), - #define MMI_LWLRC1(fp, addr, bias, off) \ - "lwl %[low32], "#bias"+"#off"("#addr") \n\t" \ - "lwr %[low32], "#bias"("#addr") \n\t" \ - "mtc1 %[low32], "#fp" \n\t" + ".set noat \n\t" \ + "lwl $at, "#bias"+"#off"("#addr") \n\t" \ + "lwr $at, "#bias"("#addr") \n\t" \ + "mtc1 $at, "#fp" \n\t" \ + ".set at \n\t" #else /* _MIPS_SIM != _ABIO32 */