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[FFmpeg-devel,v2,2/5] avutil/mips: Extract load store with shift C1 pair marco

Message ID 20210721091913.35072-3-jiaxun.yang@flygoat.com
State New
Headers show
Series avcodec Loongson-2 MMI fixes
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Commit Message

Jiaxun Yang July 21, 2021, 9:19 a.m. UTC
We're doing some fancy hacks with load store with shift C1
beside unaligned load store. Create a marco for l/r pair
to allow us use it in these places.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
 libavutil/mips/mmiutils.h | 49 ++++++++++++++++++++++++---------------
 1 file changed, 30 insertions(+), 19 deletions(-)

Comments

殷时友 July 22, 2021, 11:55 a.m. UTC | #1
&gt; -----原始邮件-----
&gt; 发件人: "Jiaxun Yang" <jiaxun.yang@flygoat.com>
&gt; 发送时间: 2021-07-21 17:19:10 (星期三)
&gt; 收件人: ffmpeg-devel@ffmpeg.org
&gt; 抄送: yinshiyou-hf@loongson.cn, "Jiaxun Yang" <jiaxun.yang@flygoat.com>
&gt; 主题: [FFmpeg-devel] [PATCH v2 2/5] avutil/mips: Extract load store with shift C1 pair marco
&gt; 
&gt; We're doing some fancy hacks with load store with shift C1
&gt; beside unaligned load store. Create a marco for l/r pair
&gt; to allow us use it in these places.
&gt; 
&gt; Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
&gt; ---
&gt;  libavutil/mips/mmiutils.h | 49 ++++++++++++++++++++++++---------------
&gt;  1 file changed, 30 insertions(+), 19 deletions(-)
&gt; 
&gt; diff --git a/libavutil/mips/mmiutils.h b/libavutil/mips/mmiutils.h
&gt; index 41715c6490..f5b600e50c 100644
&gt; --- a/libavutil/mips/mmiutils.h
&gt; +++ b/libavutil/mips/mmiutils.h
&gt; @@ -57,8 +57,9 @@
&gt;  #define MMI_LWC1(fp, addr, bias)                                            \
&gt;      "lwc1       "#fp",      "#bias"("#addr")                        \n\t"
&gt;  
&gt; -#define MMI_ULWC1(fp, addr, bias)                                           \
&gt; -    "ulw        %[low32],   "#bias"("#addr")                        \n\t"   \
&gt; +#define MMI_LWLRC1(fp, addr, bias, off)                                     \
&gt; +    "lwl        %[low32],   "#bias"+"#off"("#addr")                 \n\t"   \
&gt; +    "lwr        %[low32],   "#bias"("#addr")                        \n\t"   \
&gt;      "mtc1       %[low32],   "#fp"                                   \n\t"
&gt;  
&gt;  #define MMI_LWXC1(fp, addr, stride, bias)                                   \
&gt; @@ -68,9 +69,10 @@
&gt;  #define MMI_SWC1(fp, addr, bias)                                            \
&gt;      "swc1       "#fp",      "#bias"("#addr")                        \n\t"
&gt;  
&gt; -#define MMI_USWC1(fp, addr, bias)                                           \
&gt; +#define MMI_SWLRC1(fp, addr, bias, off)                                           \
&gt;      "mfc1       %[low32],   "#fp"                                   \n\t"   \
&gt; -    "usw        %[low32],   "#bias"("#addr")                        \n\t"
&gt; +    "swl        %[low32],   "#bias"+"#off"("#addr")                 \n\t"   \
&gt; +    "swr        %[low32],   "#bias"("#addr")                        \n\t"
&gt;  
&gt;  #define MMI_SWXC1(fp, addr, stride, bias)                                   \
&gt;      PTR_ADDU    "%[addrt],  "#addr",    "#stride"                   \n\t"   \
&gt; @@ -79,8 +81,9 @@
&gt;  #define MMI_LDC1(fp, addr, bias)                                            \
&gt;      "ldc1       "#fp",      "#bias"("#addr")                        \n\t"
&gt;  
&gt; -#define MMI_ULDC1(fp, addr, bias)                                           \
&gt; -    "uld        %[all64],   "#bias"("#addr")                        \n\t"   \
&gt; +#define MMI_LDLRC1(fp, addr, bias, off)                                     \
&gt; +    "ldl        %[all64],   "#bias"+"#off"("#addr")                 \n\t"   \
&gt; +    "ldr        %[all64],   "#bias"("#addr")                        \n\t"   \
&gt;      "dmtc1      %[all64],   "#fp"                                   \n\t"
&gt;  
&gt;  #define MMI_LDXC1(fp, addr, stride, bias)                                   \
&gt; @@ -90,9 +93,10 @@
&gt;  #define MMI_SDC1(fp, addr, bias)                                            \
&gt;      "sdc1       "#fp",      "#bias"("#addr")                        \n\t"
&gt;  
&gt; -#define MMI_USDC1(fp, addr, bias)                                           \
&gt; +#define MMI_SDLRC1(fp, addr, bias, off)                                           \
&gt;      "dmfc1      %[all64],   "#fp"                                   \n\t"   \
&gt; -    "usd        %[all64],   "#bias"("#addr")                        \n\t"
&gt; +    "sdl        %[all64],   "#bias"+"#off"("#addr")                 \n\t"   \
&gt; +    "sdr        %[all64],   "#bias"("#addr")                        \n\t"
&gt;  
&gt;  #define MMI_SDXC1(fp, addr, stride, bias)                                   \
&gt;      PTR_ADDU    "%[addrt],  "#addr",    "#stride"                   \n\t"   \
&gt; @@ -141,17 +145,18 @@
&gt;  #define DECLARE_VAR_LOW32       int32_t low32
&gt;  #define RESTRICT_ASM_LOW32      [low32]"=&amp;r"(low32),
&gt;  
&gt; -#define MMI_ULWC1(fp, addr, bias)                                           \
&gt; -    "ulw        %[low32],   "#bias"("#addr")                        \n\t"   \
&gt; -    "mtc1       %[low32],   "#fp"                                   \n\t"
&gt; +#define MMI_LWLRC1(fp, addr, bias, off)                                     \
&gt; +    "lwl        %[low32],   "#bias"+"#off"("#addr")                 \n\t"   \
&gt; +    "lwr        %[low32],   "#bias"("#addr")                        \n\t"   \
&gt; +    "mtc1       %[low32],   "#fp"                                      \n\t"
&gt;  
&gt;  #else /* _MIPS_SIM != _ABIO32 */
&gt;  
&gt;  #define DECLARE_VAR_LOW32
&gt;  #define RESTRICT_ASM_LOW32
&gt;  
&gt; -#define MMI_ULWC1(fp, addr, bias)                                           \
&gt; -    "gslwlc1    "#fp",    3+"#bias"("#addr")                        \n\t"   \
&gt; +#define MMI_LWLRC1(fp, addr, bias, off)                                     \
&gt; +    "gslwlc1    "#fp",      "#off"+"#bias"("#addr")                 \n\t"   \
&gt;      "gslwrc1    "#fp",      "#bias"("#addr")                        \n\t"
&gt;  
&gt;  #endif /* _MIPS_SIM != _ABIO32 */
&gt; @@ -162,8 +167,8 @@
&gt;  #define MMI_SWC1(fp, addr, bias)                                            \
&gt;      "swc1       "#fp",      "#bias"("#addr")                        \n\t"
&gt;  
&gt; -#define MMI_USWC1(fp, addr, bias)                                           \
&gt; -    "gsswlc1    "#fp",    3+"#bias"("#addr")                        \n\t"   \
&gt; +#define MMI_SWLRC1(fp, addr, bias, off)                                     \
&gt; +    "gsswlc1    "#fp",      "#off"+"#bias"("#addr")                 \n\t"   \
&gt;      "gsswrc1    "#fp",      "#bias"("#addr")                        \n\t"
&gt;  
&gt;  #define MMI_SWXC1(fp, addr, stride, bias)                                   \
&gt; @@ -172,8 +177,8 @@
&gt;  #define MMI_LDC1(fp, addr, bias)                                            \
&gt;      "ldc1       "#fp",      "#bias"("#addr")                        \n\t"
&gt;  
&gt; -#define MMI_ULDC1(fp, addr, bias)                                           \
&gt; -    "gsldlc1    "#fp",    7+"#bias"("#addr")                        \n\t"   \
&gt; +#define MMI_LDLRC1(fp, addr, bias, off)                                     \
&gt; +    "gsldlc1    "#fp",      "#off"+"#bias"("#addr")                 \n\t"   \
&gt;      "gsldrc1    "#fp",      "#bias"("#addr")                        \n\t"
&gt;  
&gt;  #define MMI_LDXC1(fp, addr, stride, bias)                                   \
&gt; @@ -182,8 +187,8 @@
&gt;  #define MMI_SDC1(fp, addr, bias)                                            \
&gt;      "sdc1       "#fp",      "#bias"("#addr")                        \n\t"
&gt;  
&gt; -#define MMI_USDC1(fp, addr, bias)                                           \
&gt; -    "gssdlc1    "#fp",    7+"#bias"("#addr")                        \n\t"   \
&gt; +#define MMI_SDLRC1(fp, addr, bias, off)                                           \
&gt; +    "gssdlc1    "#fp",      "#off"+"#bias"("#addr")                 \n\t"   \
&gt;      "gssdrc1    "#fp",      "#bias"("#addr")                        \n\t"
&gt;  
&gt;  #define MMI_SDXC1(fp, addr, stride, bias)                                   \
&gt; @@ -203,6 +208,12 @@
&gt;  
&gt;  #endif /* HAVE_LOONGSON2 */
&gt;  
&gt; +#define MMI_ULWC1(fp, addr, bias) MMI_LWLRC1(fp, addr, bias, 3)
&gt; +#define MMI_USWC1(fp, addr, bias) MMI_SWLRC1(fp, addr, bias, 3)
&gt; +
&gt; +#define MMI_ULDC1(fp, addr, bias) MMI_LDLRC1(fp, addr, bias, 7)
&gt; +#define MMI_USDC1(fp, addr, bias) MMI_SDLRC1(fp, addr, bias, 7)
&gt; +
&gt;  /**
&gt;   * Backup saved registers
&gt;   * We're not using compiler's clobber list as it's not smart enough
&gt; -- 
&gt; 2.32.0
&gt; 

1. Use l/r pair is a good choice.
2. Suggest keep the macro name unchanged, it's easier to use and associated with unaligned access.
3. Another 4 patches in this series are look good to me.</jiaxun.yang@flygoat.com></jiaxun.yang@flygoat.com></jiaxun.yang@flygoat.com>
Jiaxun Yang July 22, 2021, 1:59 p.m. UTC | #2
在 2021/7/22 下午7:55, yinshiyou-hf@loongson.cn 写道:
> &gt; -----原始邮件-----
> &gt; 发件人: "Jiaxun Yang" <jiaxun.yang@flygoat.com>
> &gt; 发送时间: 2021-07-21 17:19:10 (星期三)
> &gt; 收件人: ffmpeg-devel@ffmpeg.org
> &gt; 抄送: yinshiyou-hf@loongson.cn, "Jiaxun Yang" <jiaxun.yang@flygoat.com>
> &gt; 主题: [FFmpeg-devel] [PATCH v2 2/5] avutil/mips: Extract load store with shift C1 pair marco
> &gt;
> &gt; We're doing some fancy hacks with load store with shift C1
> &gt; beside unaligned load store. Create a marco for l/r pair
> &gt; to allow us use it in these places.
> &gt;
> &gt; Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
> &gt; ---
> &gt;  libavutil/mips/mmiutils.h | 49 ++++++++++++++++++++++++---------------
> &gt;  1 file changed, 30 insertions(+), 19 deletions(-)
> &gt;
> &gt; diff --git a/libavutil/mips/mmiutils.h b/libavutil/mips/mmiutils.h
> &gt; index 41715c6490..f5b600e50c 100644
> &gt; --- a/libavutil/mips/mmiutils.h
> &gt; +++ b/libavutil/mips/mmiutils.h
> &gt; @@ -57,8 +57,9 @@
> &gt;  #define MMI_LWC1(fp, addr, bias)                                            \
> &gt;      "lwc1       "#fp",      "#bias"("#addr")                        \n\t"
> &gt;
> &gt; -#define MMI_ULWC1(fp, addr, bias)                                           \
> &gt; -    "ulw        %[low32],   "#bias"("#addr")                        \n\t"   \
> &gt; +#define MMI_LWLRC1(fp, addr, bias, off)                                     \
> &gt; +    "lwl        %[low32],   "#bias"+"#off"("#addr")                 \n\t"   \
> &gt; +    "lwr        %[low32],   "#bias"("#addr")                        \n\t"   \
> &gt;      "mtc1       %[low32],   "#fp"                                   \n\t"
> &gt;
> &gt;  #define MMI_LWXC1(fp, addr, stride, bias)                                   \
> &gt; @@ -68,9 +69,10 @@
> &gt;  #define MMI_SWC1(fp, addr, bias)                                            \
> &gt;      "swc1       "#fp",      "#bias"("#addr")                        \n\t"
> &gt;
> &gt; -#define MMI_USWC1(fp, addr, bias)                                           \
> &gt; +#define MMI_SWLRC1(fp, addr, bias, off)                                           \
> &gt;      "mfc1       %[low32],   "#fp"                                   \n\t"   \
> &gt; -    "usw        %[low32],   "#bias"("#addr")                        \n\t"
> &gt; +    "swl        %[low32],   "#bias"+"#off"("#addr")                 \n\t"   \
> &gt; +    "swr        %[low32],   "#bias"("#addr")                        \n\t"
> &gt;
> &gt;  #define MMI_SWXC1(fp, addr, stride, bias)                                   \
> &gt;      PTR_ADDU    "%[addrt],  "#addr",    "#stride"                   \n\t"   \
> &gt; @@ -79,8 +81,9 @@
> &gt;  #define MMI_LDC1(fp, addr, bias)                                            \
> &gt;      "ldc1       "#fp",      "#bias"("#addr")                        \n\t"
> &gt;
> &gt; -#define MMI_ULDC1(fp, addr, bias)                                           \
> &gt; -    "uld        %[all64],   "#bias"("#addr")                        \n\t"   \
> &gt; +#define MMI_LDLRC1(fp, addr, bias, off)                                     \
> &gt; +    "ldl        %[all64],   "#bias"+"#off"("#addr")                 \n\t"   \
> &gt; +    "ldr        %[all64],   "#bias"("#addr")                        \n\t"   \
> &gt;      "dmtc1      %[all64],   "#fp"                                   \n\t"
> &gt;
> &gt;  #define MMI_LDXC1(fp, addr, stride, bias)                                   \
> &gt; @@ -90,9 +93,10 @@
> &gt;  #define MMI_SDC1(fp, addr, bias)                                            \
> &gt;      "sdc1       "#fp",      "#bias"("#addr")                        \n\t"
> &gt;
> &gt; -#define MMI_USDC1(fp, addr, bias)                                           \
> &gt; +#define MMI_SDLRC1(fp, addr, bias, off)                                           \
> &gt;      "dmfc1      %[all64],   "#fp"                                   \n\t"   \
> &gt; -    "usd        %[all64],   "#bias"("#addr")                        \n\t"
> &gt; +    "sdl        %[all64],   "#bias"+"#off"("#addr")                 \n\t"   \
> &gt; +    "sdr        %[all64],   "#bias"("#addr")                        \n\t"
> &gt;
> &gt;  #define MMI_SDXC1(fp, addr, stride, bias)                                   \
> &gt;      PTR_ADDU    "%[addrt],  "#addr",    "#stride"                   \n\t"   \
> &gt; @@ -141,17 +145,18 @@
> &gt;  #define DECLARE_VAR_LOW32       int32_t low32
> &gt;  #define RESTRICT_ASM_LOW32      [low32]"=&amp;r"(low32),
> &gt;
> &gt; -#define MMI_ULWC1(fp, addr, bias)                                           \
> &gt; -    "ulw        %[low32],   "#bias"("#addr")                        \n\t"   \
> &gt; -    "mtc1       %[low32],   "#fp"                                   \n\t"
> &gt; +#define MMI_LWLRC1(fp, addr, bias, off)                                     \
> &gt; +    "lwl        %[low32],   "#bias"+"#off"("#addr")                 \n\t"   \
> &gt; +    "lwr        %[low32],   "#bias"("#addr")                        \n\t"   \
> &gt; +    "mtc1       %[low32],   "#fp"                                      \n\t"
> &gt;
> &gt;  #else /* _MIPS_SIM != _ABIO32 */
> &gt;
> &gt;  #define DECLARE_VAR_LOW32
> &gt;  #define RESTRICT_ASM_LOW32
> &gt;
> &gt; -#define MMI_ULWC1(fp, addr, bias)                                           \
> &gt; -    "gslwlc1    "#fp",    3+"#bias"("#addr")                        \n\t"   \
> &gt; +#define MMI_LWLRC1(fp, addr, bias, off)                                     \
> &gt; +    "gslwlc1    "#fp",      "#off"+"#bias"("#addr")                 \n\t"   \
> &gt;      "gslwrc1    "#fp",      "#bias"("#addr")                        \n\t"
> &gt;
> &gt;  #endif /* _MIPS_SIM != _ABIO32 */
> &gt; @@ -162,8 +167,8 @@
> &gt;  #define MMI_SWC1(fp, addr, bias)                                            \
> &gt;      "swc1       "#fp",      "#bias"("#addr")                        \n\t"
> &gt;
> &gt; -#define MMI_USWC1(fp, addr, bias)                                           \
> &gt; -    "gsswlc1    "#fp",    3+"#bias"("#addr")                        \n\t"   \
> &gt; +#define MMI_SWLRC1(fp, addr, bias, off)                                     \
> &gt; +    "gsswlc1    "#fp",      "#off"+"#bias"("#addr")                 \n\t"   \
> &gt;      "gsswrc1    "#fp",      "#bias"("#addr")                        \n\t"
> &gt;
> &gt;  #define MMI_SWXC1(fp, addr, stride, bias)                                   \
> &gt; @@ -172,8 +177,8 @@
> &gt;  #define MMI_LDC1(fp, addr, bias)                                            \
> &gt;      "ldc1       "#fp",      "#bias"("#addr")                        \n\t"
> &gt;
> &gt; -#define MMI_ULDC1(fp, addr, bias)                                           \
> &gt; -    "gsldlc1    "#fp",    7+"#bias"("#addr")                        \n\t"   \
> &gt; +#define MMI_LDLRC1(fp, addr, bias, off)                                     \
> &gt; +    "gsldlc1    "#fp",      "#off"+"#bias"("#addr")                 \n\t"   \
> &gt;      "gsldrc1    "#fp",      "#bias"("#addr")                        \n\t"
> &gt;
> &gt;  #define MMI_LDXC1(fp, addr, stride, bias)                                   \
> &gt; @@ -182,8 +187,8 @@
> &gt;  #define MMI_SDC1(fp, addr, bias)                                            \
> &gt;      "sdc1       "#fp",      "#bias"("#addr")                        \n\t"
> &gt;
> &gt; -#define MMI_USDC1(fp, addr, bias)                                           \
> &gt; -    "gssdlc1    "#fp",    7+"#bias"("#addr")                        \n\t"   \
> &gt; +#define MMI_SDLRC1(fp, addr, bias, off)                                           \
> &gt; +    "gssdlc1    "#fp",      "#off"+"#bias"("#addr")                 \n\t"   \
> &gt;      "gssdrc1    "#fp",      "#bias"("#addr")                        \n\t"
> &gt;
> &gt;  #define MMI_SDXC1(fp, addr, stride, bias)                                   \
> &gt; @@ -203,6 +208,12 @@
> &gt;
> &gt;  #endif /* HAVE_LOONGSON2 */
> &gt;
> &gt; +#define MMI_ULWC1(fp, addr, bias) MMI_LWLRC1(fp, addr, bias, 3)
> &gt; +#define MMI_USWC1(fp, addr, bias) MMI_SWLRC1(fp, addr, bias, 3)
> &gt; +
> &gt; +#define MMI_ULDC1(fp, addr, bias) MMI_LDLRC1(fp, addr, bias, 7)
> &gt; +#define MMI_USDC1(fp, addr, bias) MMI_SDLRC1(fp, addr, bias, 7)
> &gt; +
> &gt;  /**
> &gt;   * Backup saved registers
> &gt;   * We're not using compiler's clobber list as it's not smart enough
> &gt; --
> &gt; 2.32.0
> &gt;
>
> 1. Use l/r pair is a good choice.
> 2. Suggest keep the macro name unchanged, it's easier to use and associated with unaligned access.

Hmm, the name of {MMI_ULDC1, MMI_USDC1} is actually unchanged, what do 
you meant by macro name?

Thanks.


- Jiaxun

> 3. Another 4 patches in this series are look good to me.</jiaxun.yang@flygoat.com></jiaxun.yang@flygoat.com></jiaxun.yang@flygoat.com>
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殷时友 July 23, 2021, 3:59 a.m. UTC | #3
&gt; -----原始邮件-----
&gt; 发件人: "Jiaxun Yang" <jiaxun.yang@flygoat.com>
&gt; 发送时间: 2021-07-22 21:59:03 (星期四)
&gt; 收件人: ffmpeg-devel@ffmpeg.org
&gt; 抄送: 
&gt; 主题: Re: [FFmpeg-devel] [PATCH v2 2/5] avutil/mips: Extract load store with shift C1 pair marco
&gt; 
&gt; 
&gt; 在 2021/7/22 下午7:55, yinshiyou-hf@loongson.cn 写道:
&gt; &gt; &gt; -----原始邮件-----
&gt; &gt; &gt; 发件人: "Jiaxun Yang" <jiaxun.yang@flygoat.com>
&gt; &gt; &gt; 发送时间: 2021-07-21 17:19:10 (星期三)
&gt; &gt; &gt; 收件人: ffmpeg-devel@ffmpeg.org
&gt; &gt; &gt; 抄送: yinshiyou-hf@loongson.cn, "Jiaxun Yang" <jiaxun.yang@flygoat.com>
&gt; &gt; &gt; 主题: [FFmpeg-devel] [PATCH v2 2/5] avutil/mips: Extract load store with shift C1 pair marco
&gt; &gt; &gt;
&gt; &gt; &gt; We're doing some fancy hacks with load store with shift C1
&gt; &gt; &gt; beside unaligned load store. Create a marco for l/r pair
&gt; &gt; &gt; to allow us use it in these places.
&gt; &gt; &gt;
&gt; &gt; &gt; Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
&gt; &gt; &gt; ---
&gt; &gt; &gt;  libavutil/mips/mmiutils.h | 49 ++++++++++++++++++++++++---------------
&gt; &gt; &gt;  1 file changed, 30 insertions(+), 19 deletions(-)
&gt; &gt; &gt;
&gt; &gt; &gt; diff --git a/libavutil/mips/mmiutils.h b/libavutil/mips/mmiutils.h
&gt; &gt; &gt; index 41715c6490..f5b600e50c 100644
&gt; &gt; &gt; --- a/libavutil/mips/mmiutils.h
&gt; &gt; &gt; +++ b/libavutil/mips/mmiutils.h
&gt; &gt; &gt; @@ -57,8 +57,9 @@
&gt; &gt; &gt;  #define MMI_LWC1(fp, addr, bias)                                            \
&gt; &gt; &gt;      "lwc1       "#fp",      "#bias"("#addr")                        \n\t"
&gt; &gt; &gt;
&gt; &gt; &gt; -#define MMI_ULWC1(fp, addr, bias)                                           \
&gt; &gt; &gt; -    "ulw        %[low32],   "#bias"("#addr")                        \n\t"   \
&gt; &gt; &gt; +#define MMI_LWLRC1(fp, addr, bias, off)                                     \
&gt; &gt; &gt; +    "lwl        %[low32],   "#bias"+"#off"("#addr")                 \n\t"   \
&gt; &gt; &gt; +    "lwr        %[low32],   "#bias"("#addr")                        \n\t"   \
&gt; &gt; &gt;      "mtc1       %[low32],   "#fp"                                   \n\t"
&gt; &gt; &gt;
&gt; &gt; &gt;  #define MMI_LWXC1(fp, addr, stride, bias)                                   \
&gt; &gt; &gt; @@ -68,9 +69,10 @@
&gt; &gt; &gt;  #define MMI_SWC1(fp, addr, bias)                                            \
&gt; &gt; &gt;      "swc1       "#fp",      "#bias"("#addr")                        \n\t"
&gt; &gt; &gt;
&gt; &gt; &gt; -#define MMI_USWC1(fp, addr, bias)                                           \
&gt; &gt; &gt; +#define MMI_SWLRC1(fp, addr, bias, off)                                           \
&gt; &gt; &gt;      "mfc1       %[low32],   "#fp"                                   \n\t"   \
&gt; &gt; &gt; -    "usw        %[low32],   "#bias"("#addr")                        \n\t"
&gt; &gt; &gt; +    "swl        %[low32],   "#bias"+"#off"("#addr")                 \n\t"   \
&gt; &gt; &gt; +    "swr        %[low32],   "#bias"("#addr")                        \n\t"
&gt; &gt; &gt;
&gt; &gt; &gt;  #define MMI_SWXC1(fp, addr, stride, bias)                                   \
&gt; &gt; &gt;      PTR_ADDU    "%[addrt],  "#addr",    "#stride"                   \n\t"   \
&gt; &gt; &gt; @@ -79,8 +81,9 @@
&gt; &gt; &gt;  #define MMI_LDC1(fp, addr, bias)                                            \
&gt; &gt; &gt;      "ldc1       "#fp",      "#bias"("#addr")                        \n\t"
&gt; &gt; &gt;
&gt; &gt; &gt; -#define MMI_ULDC1(fp, addr, bias)                                           \
&gt; &gt; &gt; -    "uld        %[all64],   "#bias"("#addr")                        \n\t"   \
&gt; &gt; &gt; +#define MMI_LDLRC1(fp, addr, bias, off)                                     \
&gt; &gt; &gt; +    "ldl        %[all64],   "#bias"+"#off"("#addr")                 \n\t"   \
&gt; &gt; &gt; +    "ldr        %[all64],   "#bias"("#addr")                        \n\t"   \
&gt; &gt; &gt;      "dmtc1      %[all64],   "#fp"                                   \n\t"
&gt; &gt; &gt;
&gt; &gt; &gt;  #define MMI_LDXC1(fp, addr, stride, bias)                                   \
&gt; &gt; &gt; @@ -90,9 +93,10 @@
&gt; &gt; &gt;  #define MMI_SDC1(fp, addr, bias)                                            \
&gt; &gt; &gt;      "sdc1       "#fp",      "#bias"("#addr")                        \n\t"
&gt; &gt; &gt;
&gt; &gt; &gt; -#define MMI_USDC1(fp, addr, bias)                                           \
&gt; &gt; &gt; +#define MMI_SDLRC1(fp, addr, bias, off)                                           \
&gt; &gt; &gt;      "dmfc1      %[all64],   "#fp"                                   \n\t"   \
&gt; &gt; &gt; -    "usd        %[all64],   "#bias"("#addr")                        \n\t"
&gt; &gt; &gt; +    "sdl        %[all64],   "#bias"+"#off"("#addr")                 \n\t"   \
&gt; &gt; &gt; +    "sdr        %[all64],   "#bias"("#addr")                        \n\t"
&gt; &gt; &gt;
&gt; &gt; &gt;  #define MMI_SDXC1(fp, addr, stride, bias)                                   \
&gt; &gt; &gt;      PTR_ADDU    "%[addrt],  "#addr",    "#stride"                   \n\t"   \
&gt; &gt; &gt; @@ -141,17 +145,18 @@
&gt; &gt; &gt;  #define DECLARE_VAR_LOW32       int32_t low32
&gt; &gt; &gt;  #define RESTRICT_ASM_LOW32      [low32]"=&amp;r"(low32),
&gt; &gt; &gt;
&gt; &gt; &gt; -#define MMI_ULWC1(fp, addr, bias)                                           \
&gt; &gt; &gt; -    "ulw        %[low32],   "#bias"("#addr")                        \n\t"   \
&gt; &gt; &gt; -    "mtc1       %[low32],   "#fp"                                   \n\t"
&gt; &gt; &gt; +#define MMI_LWLRC1(fp, addr, bias, off)                                     \
&gt; &gt; &gt; +    "lwl        %[low32],   "#bias"+"#off"("#addr")                 \n\t"   \
&gt; &gt; &gt; +    "lwr        %[low32],   "#bias"("#addr")                        \n\t"   \
&gt; &gt; &gt; +    "mtc1       %[low32],   "#fp"                                      \n\t"
&gt; &gt; &gt;
&gt; &gt; &gt;  #else /* _MIPS_SIM != _ABIO32 */
&gt; &gt; &gt;
&gt; &gt; &gt;  #define DECLARE_VAR_LOW32
&gt; &gt; &gt;  #define RESTRICT_ASM_LOW32
&gt; &gt; &gt;
&gt; &gt; &gt; -#define MMI_ULWC1(fp, addr, bias)                                           \
&gt; &gt; &gt; -    "gslwlc1    "#fp",    3+"#bias"("#addr")                        \n\t"   \
&gt; &gt; &gt; +#define MMI_LWLRC1(fp, addr, bias, off)                                     \
&gt; &gt; &gt; +    "gslwlc1    "#fp",      "#off"+"#bias"("#addr")                 \n\t"   \
&gt; &gt; &gt;      "gslwrc1    "#fp",      "#bias"("#addr")                        \n\t"
&gt; &gt; &gt;
&gt; &gt; &gt;  #endif /* _MIPS_SIM != _ABIO32 */
&gt; &gt; &gt; @@ -162,8 +167,8 @@
&gt; &gt; &gt;  #define MMI_SWC1(fp, addr, bias)                                            \
&gt; &gt; &gt;      "swc1       "#fp",      "#bias"("#addr")                        \n\t"
&gt; &gt; &gt;
&gt; &gt; &gt; -#define MMI_USWC1(fp, addr, bias)                                           \
&gt; &gt; &gt; -    "gsswlc1    "#fp",    3+"#bias"("#addr")                        \n\t"   \
&gt; &gt; &gt; +#define MMI_SWLRC1(fp, addr, bias, off)                                     \
&gt; &gt; &gt; +    "gsswlc1    "#fp",      "#off"+"#bias"("#addr")                 \n\t"   \
&gt; &gt; &gt;      "gsswrc1    "#fp",      "#bias"("#addr")                        \n\t"
&gt; &gt; &gt;
&gt; &gt; &gt;  #define MMI_SWXC1(fp, addr, stride, bias)                                   \
&gt; &gt; &gt; @@ -172,8 +177,8 @@
&gt; &gt; &gt;  #define MMI_LDC1(fp, addr, bias)                                            \
&gt; &gt; &gt;      "ldc1       "#fp",      "#bias"("#addr")                        \n\t"
&gt; &gt; &gt;
&gt; &gt; &gt; -#define MMI_ULDC1(fp, addr, bias)                                           \
&gt; &gt; &gt; -    "gsldlc1    "#fp",    7+"#bias"("#addr")                        \n\t"   \
&gt; &gt; &gt; +#define MMI_LDLRC1(fp, addr, bias, off)                                     \
&gt; &gt; &gt; +    "gsldlc1    "#fp",      "#off"+"#bias"("#addr")                 \n\t"   \
&gt; &gt; &gt;      "gsldrc1    "#fp",      "#bias"("#addr")                        \n\t"
&gt; &gt; &gt;
&gt; &gt; &gt;  #define MMI_LDXC1(fp, addr, stride, bias)                                   \
&gt; &gt; &gt; @@ -182,8 +187,8 @@
&gt; &gt; &gt;  #define MMI_SDC1(fp, addr, bias)                                            \
&gt; &gt; &gt;      "sdc1       "#fp",      "#bias"("#addr")                        \n\t"
&gt; &gt; &gt;
&gt; &gt; &gt; -#define MMI_USDC1(fp, addr, bias)                                           \
&gt; &gt; &gt; -    "gssdlc1    "#fp",    7+"#bias"("#addr")                        \n\t"   \
&gt; &gt; &gt; +#define MMI_SDLRC1(fp, addr, bias, off)                                           \
&gt; &gt; &gt; +    "gssdlc1    "#fp",      "#off"+"#bias"("#addr")                 \n\t"   \
&gt; &gt; &gt;      "gssdrc1    "#fp",      "#bias"("#addr")                        \n\t"
&gt; &gt; &gt;
&gt; &gt; &gt;  #define MMI_SDXC1(fp, addr, stride, bias)                                   \
&gt; &gt; &gt; @@ -203,6 +208,12 @@
&gt; &gt; &gt;
&gt; &gt; &gt;  #endif /* HAVE_LOONGSON2 */
&gt; &gt; &gt;
&gt; &gt; &gt; +#define MMI_ULWC1(fp, addr, bias) MMI_LWLRC1(fp, addr, bias, 3)
&gt; &gt; &gt; +#define MMI_USWC1(fp, addr, bias) MMI_SWLRC1(fp, addr, bias, 3)
&gt; &gt; &gt; +
&gt; &gt; &gt; +#define MMI_ULDC1(fp, addr, bias) MMI_LDLRC1(fp, addr, bias, 7)
&gt; &gt; &gt; +#define MMI_USDC1(fp, addr, bias) MMI_SDLRC1(fp, addr, bias, 7)
&gt; &gt; &gt; +
&gt; &gt; &gt;  /**
&gt; &gt; &gt;   * Backup saved registers
&gt; &gt; &gt;   * We're not using compiler's clobber list as it's not smart enough
&gt; &gt; &gt; --
&gt; &gt; &gt; 2.32.0
&gt; &gt; &gt;
&gt; &gt;
&gt; &gt; 1. Use l/r pair is a good choice.
&gt; &gt; 2. Suggest keep the macro name unchanged, it's easier to use and associated with unaligned access.
&gt; 
&gt; Hmm, the name of {MMI_ULDC1, MMI_USDC1} is actually unchanged, what do 
&gt; you meant by macro name?
&gt; 
&gt; Thanks.
&gt; 
&gt; 
For your reference.

diff --git a/libavutil/mips/mmiutils.h b/libavutil/mips/mmiutils.h
index 6a82caa..28fa8cf 100644
--- a/libavutil/mips/mmiutils.h
+++ b/libavutil/mips/mmiutils.h
@@ -58,7 +58,8 @@
     "lwc1       "#fp",      "#bias"("#addr")                        \n\t"
 
 #define MMI_ULWC1(fp, addr, bias)                                           \
-    "ulw        %[low32],   "#bias"("#addr")                        \n\t"   \
+    "lwl        %[low32],   3 + "#bias"("#addr")                    \n\t"   \
+    "lwr        %[low32],   "#bias"("#addr")                        \n\t"   \
     "mtc1       %[low32],   "#fp"                                   \n\t"
 
 #define MMI_LWXC1(fp, addr, stride, bias)                                   \
@@ -70,7 +71,8 @@
 
 #define MMI_USWC1(fp, addr, bias)                                           \
     "mfc1       %[low32],   "#fp"                                   \n\t"   \
-    "usw        %[low32],   "#bias"("#addr")                        \n\t"
+    "swl        %[low32],   3 + "#bias"("#addr")                    \n\t"   \
+    "swr        %[low32],   "#bias"("#addr")                        \n\t"
 
 #define MMI_SWXC1(fp, addr, stride, bias)                                   \
     PTR_ADDU    "%[addrt],  "#addr",    "#stride"                   \n\t"   \
@@ -80,7 +82,8 @@
     "ldc1       "#fp",      "#bias"("#addr")                        \n\t"
 
 #define MMI_ULDC1(fp, addr, bias)                                           \
-    "uld        %[all64],   "#bias"("#addr")                        \n\t"   \
+    "ldl        %[all64],   7 + "#bias"("#addr")                    \n\t"   \
+    "ldr        %[all64],   "#bias"("#addr")                        \n\t"   \
     "dmtc1      %[all64],   "#fp"                                   \n\t"
 
 #define MMI_LDXC1(fp, addr, stride, bias)                                   \
@@ -92,7 +95,8 @@
 
 #define MMI_USDC1(fp, addr, bias)                                           \
     "dmfc1      %[all64],   "#fp"                                   \n\t"   \
-    "usd        %[all64],   "#bias"("#addr")                        \n\t"
+    "sdl        %[all64],   7 + "#bias"("#addr")                    \n\t"   \
+    "sdr        %[all64],   "#bias"("#addr")                        \n\t"
 
 #define MMI_SDXC1(fp, addr, stride, bias)                                   \
     PTR_ADDU    "%[addrt],  "#addr",    "#stride"                   \n\t"   \
@@ -142,7 +146,8 @@
 #define RESTRICT_ASM_LOW32      [low32]"=&amp;r"(low32),
 
 #define MMI_ULWC1(fp, addr, bias)                                           \
-    "ulw        %[low32],   "#bias"("#addr")                        \n\t"   \
+    "lwl        %[low32],   3 + "#bias"("#addr")                    \n\t"   \
+    "lwr        %[low32],   "#bias"("#addr")                        \n\t"   \
     "mtc1       %[low32],   "#fp"                                   \n\t"
 
 #else /* _MIPS_SIM != _ABIO32 */
</jiaxun.yang@flygoat.com></jiaxun.yang@flygoat.com></jiaxun.yang@flygoat.com></jiaxun.yang@flygoat.com>
Jiaxun Yang July 23, 2021, 5:51 a.m. UTC | #4
在 2021/7/23 上午11:59, yinshiyou-hf@loongson.cn 写道:
> &gt; -----原始邮件-----
> &gt; 发件人: "Jiaxun Yang" <jiaxun.yang@flygoat.com>
> &gt; 发送时间: 2021-07-22 21:59:03 (星期四)
> &gt; 收件人: ffmpeg-devel@ffmpeg.org
> &gt; 抄送:
> &gt; 主题: Re: [FFmpeg-devel] [PATCH v2 2/5] avutil/mips: Extract load store with shift C1 pair marco
> &gt;
> &gt;
> &gt; 在 2021/7/22 下午7:55, yinshiyou-hf@loongson.cn 写道:
> &gt; &gt; &gt; -----原始邮件-----
> &gt; &gt; &gt; 发件人: "Jiaxun Yang" <jiaxun.yang@flygoat.com>
> &gt; &gt; &gt; 发送时间: 2021-07-21 17:19:10 (星期三)
> &gt; &gt; &gt; 收件人: ffmpeg-devel@ffmpeg.org
> &gt; &gt; &gt; 抄送: yinshiyou-hf@loongson.cn, "Jiaxun Yang" <jiaxun.yang@flygoat.com>
> &gt; &gt; &gt; 主题: [FFmpeg-devel] [PATCH v2 2/5] avutil/mips: Extract load store with shift C1 pair marco
> &gt; &gt; &gt;
> &gt; &gt; &gt; We're doing some fancy hacks with load store with shift C1
> &gt; &gt; &gt; beside unaligned load store. Create a marco for l/r pair
> &gt; &gt; &gt; to allow us use it in these places.
> &gt; &gt; &gt;
> &gt; &gt; &gt; Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
> &gt; &gt; &gt; ---
> &gt; &gt; &gt;  libavutil/mips/mmiutils.h | 49 ++++++++++++++++++++++++---------------
> &gt; &gt; &gt;  1 file changed, 30 insertions(+), 19 deletions(-)
> &gt; &gt; &gt;
> &gt; &gt; &gt; diff --git a/libavutil/mips/mmiutils.h b/libavutil/mips/mmiutils.h
> &gt; &gt; &gt; index 41715c6490..f5b600e50c 100644
> &gt; &gt; &gt; --- a/libavutil/mips/mmiutils.h
> &gt; &gt; &gt; +++ b/libavutil/mips/mmiutils.h
> &gt; &gt; &gt; @@ -57,8 +57,9 @@
> &gt; &gt; &gt;  #define MMI_LWC1(fp, addr, bias)                                            \
> &gt; &gt; &gt;      "lwc1       "#fp",      "#bias"("#addr")                        \n\t"
> &gt; &gt; &gt;
> &gt; &gt; &gt; -#define MMI_ULWC1(fp, addr, bias)                                           \
> &gt; &gt; &gt; -    "ulw        %[low32],   "#bias"("#addr")                        \n\t"   \
> &gt; &gt; &gt; +#define MMI_LWLRC1(fp, addr, bias, off)                                     \
> &gt; &gt; &gt; +    "lwl        %[low32],   "#bias"+"#off"("#addr")                 \n\t"   \
> &gt; &gt; &gt; +    "lwr        %[low32],   "#bias"("#addr")                        \n\t"   \
> &gt; &gt; &gt;      "mtc1       %[low32],   "#fp"                                   \n\t"
> &gt; &gt; &gt;
> &gt; &gt; &gt;  #define MMI_LWXC1(fp, addr, stride, bias)                                   \
> &gt; &gt; &gt; @@ -68,9 +69,10 @@
> &gt; &gt; &gt;  #define MMI_SWC1(fp, addr, bias)                                            \
> &gt; &gt; &gt;      "swc1       "#fp",      "#bias"("#addr")                        \n\t"
> &gt; &gt; &gt;
> &gt; &gt; &gt; -#define MMI_USWC1(fp, addr, bias)                                           \
> &gt; &gt; &gt; +#define MMI_SWLRC1(fp, addr, bias, off)                                           \
> &gt; &gt; &gt;      "mfc1       %[low32],   "#fp"                                   \n\t"   \
> &gt; &gt; &gt; -    "usw        %[low32],   "#bias"("#addr")                        \n\t"
> &gt; &gt; &gt; +    "swl        %[low32],   "#bias"+"#off"("#addr")                 \n\t"   \
> &gt; &gt; &gt; +    "swr        %[low32],   "#bias"("#addr")                        \n\t"
> &gt; &gt; &gt;
> &gt; &gt; &gt;  #define MMI_SWXC1(fp, addr, stride, bias)                                   \
> &gt; &gt; &gt;      PTR_ADDU    "%[addrt],  "#addr",    "#stride"                   \n\t"   \
> &gt; &gt; &gt; @@ -79,8 +81,9 @@
> &gt; &gt; &gt;  #define MMI_LDC1(fp, addr, bias)                                            \
> &gt; &gt; &gt;      "ldc1       "#fp",      "#bias"("#addr")                        \n\t"
> &gt; &gt; &gt;
> &gt; &gt; &gt; -#define MMI_ULDC1(fp, addr, bias)                                           \
> &gt; &gt; &gt; -    "uld        %[all64],   "#bias"("#addr")                        \n\t"   \
> &gt; &gt; &gt; +#define MMI_LDLRC1(fp, addr, bias, off)                                     \
> &gt; &gt; &gt; +    "ldl        %[all64],   "#bias"+"#off"("#addr")                 \n\t"   \
> &gt; &gt; &gt; +    "ldr        %[all64],   "#bias"("#addr")                        \n\t"   \
> &gt; &gt; &gt;      "dmtc1      %[all64],   "#fp"                                   \n\t"
> &gt; &gt; &gt;
> &gt; &gt; &gt;  #define MMI_LDXC1(fp, addr, stride, bias)                                   \
> &gt; &gt; &gt; @@ -90,9 +93,10 @@
> &gt; &gt; &gt;  #define MMI_SDC1(fp, addr, bias)                                            \
> &gt; &gt; &gt;      "sdc1       "#fp",      "#bias"("#addr")                        \n\t"
> &gt; &gt; &gt;
> &gt; &gt; &gt; -#define MMI_USDC1(fp, addr, bias)                                           \
> &gt; &gt; &gt; +#define MMI_SDLRC1(fp, addr, bias, off)                                           \
> &gt; &gt; &gt;      "dmfc1      %[all64],   "#fp"                                   \n\t"   \
> &gt; &gt; &gt; -    "usd        %[all64],   "#bias"("#addr")                        \n\t"
> &gt; &gt; &gt; +    "sdl        %[all64],   "#bias"+"#off"("#addr")                 \n\t"   \
> &gt; &gt; &gt; +    "sdr        %[all64],   "#bias"("#addr")                        \n\t"
> &gt; &gt; &gt;
> &gt; &gt; &gt;  #define MMI_SDXC1(fp, addr, stride, bias)                                   \
> &gt; &gt; &gt;      PTR_ADDU    "%[addrt],  "#addr",    "#stride"                   \n\t"   \
> &gt; &gt; &gt; @@ -141,17 +145,18 @@
> &gt; &gt; &gt;  #define DECLARE_VAR_LOW32       int32_t low32
> &gt; &gt; &gt;  #define RESTRICT_ASM_LOW32      [low32]"=&amp;r"(low32),
> &gt; &gt; &gt;
> &gt; &gt; &gt; -#define MMI_ULWC1(fp, addr, bias)                                           \
> &gt; &gt; &gt; -    "ulw        %[low32],   "#bias"("#addr")                        \n\t"   \
> &gt; &gt; &gt; -    "mtc1       %[low32],   "#fp"                                   \n\t"
> &gt; &gt; &gt; +#define MMI_LWLRC1(fp, addr, bias, off)                                     \
> &gt; &gt; &gt; +    "lwl        %[low32],   "#bias"+"#off"("#addr")                 \n\t"   \
> &gt; &gt; &gt; +    "lwr        %[low32],   "#bias"("#addr")                        \n\t"   \
> &gt; &gt; &gt; +    "mtc1       %[low32],   "#fp"                                      \n\t"
> &gt; &gt; &gt;
> &gt; &gt; &gt;  #else /* _MIPS_SIM != _ABIO32 */
> &gt; &gt; &gt;
> &gt; &gt; &gt;  #define DECLARE_VAR_LOW32
> &gt; &gt; &gt;  #define RESTRICT_ASM_LOW32
> &gt; &gt; &gt;
> &gt; &gt; &gt; -#define MMI_ULWC1(fp, addr, bias)                                           \
> &gt; &gt; &gt; -    "gslwlc1    "#fp",    3+"#bias"("#addr")                        \n\t"   \
> &gt; &gt; &gt; +#define MMI_LWLRC1(fp, addr, bias, off)                                     \
> &gt; &gt; &gt; +    "gslwlc1    "#fp",      "#off"+"#bias"("#addr")                 \n\t"   \
> &gt; &gt; &gt;      "gslwrc1    "#fp",      "#bias"("#addr")                        \n\t"
> &gt; &gt; &gt;
> &gt; &gt; &gt;  #endif /* _MIPS_SIM != _ABIO32 */
> &gt; &gt; &gt; @@ -162,8 +167,8 @@
> &gt; &gt; &gt;  #define MMI_SWC1(fp, addr, bias)                                            \
> &gt; &gt; &gt;      "swc1       "#fp",      "#bias"("#addr")                        \n\t"
> &gt; &gt; &gt;
> &gt; &gt; &gt; -#define MMI_USWC1(fp, addr, bias)                                           \
> &gt; &gt; &gt; -    "gsswlc1    "#fp",    3+"#bias"("#addr")                        \n\t"   \
> &gt; &gt; &gt; +#define MMI_SWLRC1(fp, addr, bias, off)                                     \
> &gt; &gt; &gt; +    "gsswlc1    "#fp",      "#off"+"#bias"("#addr")                 \n\t"   \
> &gt; &gt; &gt;      "gsswrc1    "#fp",      "#bias"("#addr")                        \n\t"
> &gt; &gt; &gt;
> &gt; &gt; &gt;  #define MMI_SWXC1(fp, addr, stride, bias)                                   \
> &gt; &gt; &gt; @@ -172,8 +177,8 @@
> &gt; &gt; &gt;  #define MMI_LDC1(fp, addr, bias)                                            \
> &gt; &gt; &gt;      "ldc1       "#fp",      "#bias"("#addr")                        \n\t"
> &gt; &gt; &gt;
> &gt; &gt; &gt; -#define MMI_ULDC1(fp, addr, bias)                                           \
> &gt; &gt; &gt; -    "gsldlc1    "#fp",    7+"#bias"("#addr")                        \n\t"   \
> &gt; &gt; &gt; +#define MMI_LDLRC1(fp, addr, bias, off)                                     \
> &gt; &gt; &gt; +    "gsldlc1    "#fp",      "#off"+"#bias"("#addr")                 \n\t"   \
> &gt; &gt; &gt;      "gsldrc1    "#fp",      "#bias"("#addr")                        \n\t"
> &gt; &gt; &gt;
> &gt; &gt; &gt;  #define MMI_LDXC1(fp, addr, stride, bias)                                   \
> &gt; &gt; &gt; @@ -182,8 +187,8 @@
> &gt; &gt; &gt;  #define MMI_SDC1(fp, addr, bias)                                            \
> &gt; &gt; &gt;      "sdc1       "#fp",      "#bias"("#addr")                        \n\t"
> &gt; &gt; &gt;
> &gt; &gt; &gt; -#define MMI_USDC1(fp, addr, bias)                                           \
> &gt; &gt; &gt; -    "gssdlc1    "#fp",    7+"#bias"("#addr")                        \n\t"   \
> &gt; &gt; &gt; +#define MMI_SDLRC1(fp, addr, bias, off)                                           \
> &gt; &gt; &gt; +    "gssdlc1    "#fp",      "#off"+"#bias"("#addr")                 \n\t"   \
> &gt; &gt; &gt;      "gssdrc1    "#fp",      "#bias"("#addr")                        \n\t"
> &gt; &gt; &gt;
> &gt; &gt; &gt;  #define MMI_SDXC1(fp, addr, stride, bias)                                   \
> &gt; &gt; &gt; @@ -203,6 +208,12 @@
> &gt; &gt; &gt;
> &gt; &gt; &gt;  #endif /* HAVE_LOONGSON2 */
> &gt; &gt; &gt;
> &gt; &gt; &gt; +#define MMI_ULWC1(fp, addr, bias) MMI_LWLRC1(fp, addr, bias, 3)
> &gt; &gt; &gt; +#define MMI_USWC1(fp, addr, bias) MMI_SWLRC1(fp, addr, bias, 3)
> &gt; &gt; &gt; +
> &gt; &gt; &gt; +#define MMI_ULDC1(fp, addr, bias) MMI_LDLRC1(fp, addr, bias, 7)
> &gt; &gt; &gt; +#define MMI_USDC1(fp, addr, bias) MMI_SDLRC1(fp, addr, bias, 7)
> &gt; &gt; &gt; +
> &gt; &gt; &gt;  /**
> &gt; &gt; &gt;   * Backup saved registers
> &gt; &gt; &gt;   * We're not using compiler's clobber list as it's not smart enough
> &gt; &gt; &gt; --
> &gt; &gt; &gt; 2.32.0
> &gt; &gt; &gt;
> &gt; &gt;
> &gt; &gt; 1. Use l/r pair is a good choice.
> &gt; &gt; 2. Suggest keep the macro name unchanged, it's easier to use and associated with unaligned access.
> &gt;
> &gt; Hmm, the name of {MMI_ULDC1, MMI_USDC1} is actually unchanged, what do
> &gt; you meant by macro name?
> &gt;
> &gt; Thanks.
> &gt;
> &gt;
> For your reference.

Thanks for your advice!

However I found that the issue I was trying to resolve with this patch 
was resolved in binutils. So I can simply drop this patch.

I'm going to resend the series with your review tag.

Thanks.

- Jiaxun
diff mbox series

Patch

diff --git a/libavutil/mips/mmiutils.h b/libavutil/mips/mmiutils.h
index 41715c6490..f5b600e50c 100644
--- a/libavutil/mips/mmiutils.h
+++ b/libavutil/mips/mmiutils.h
@@ -57,8 +57,9 @@ 
 #define MMI_LWC1(fp, addr, bias)                                            \
     "lwc1       "#fp",      "#bias"("#addr")                        \n\t"
 
-#define MMI_ULWC1(fp, addr, bias)                                           \
-    "ulw        %[low32],   "#bias"("#addr")                        \n\t"   \
+#define MMI_LWLRC1(fp, addr, bias, off)                                     \
+    "lwl        %[low32],   "#bias"+"#off"("#addr")                 \n\t"   \
+    "lwr        %[low32],   "#bias"("#addr")                        \n\t"   \
     "mtc1       %[low32],   "#fp"                                   \n\t"
 
 #define MMI_LWXC1(fp, addr, stride, bias)                                   \
@@ -68,9 +69,10 @@ 
 #define MMI_SWC1(fp, addr, bias)                                            \
     "swc1       "#fp",      "#bias"("#addr")                        \n\t"
 
-#define MMI_USWC1(fp, addr, bias)                                           \
+#define MMI_SWLRC1(fp, addr, bias, off)                                           \
     "mfc1       %[low32],   "#fp"                                   \n\t"   \
-    "usw        %[low32],   "#bias"("#addr")                        \n\t"
+    "swl        %[low32],   "#bias"+"#off"("#addr")                 \n\t"   \
+    "swr        %[low32],   "#bias"("#addr")                        \n\t"
 
 #define MMI_SWXC1(fp, addr, stride, bias)                                   \
     PTR_ADDU    "%[addrt],  "#addr",    "#stride"                   \n\t"   \
@@ -79,8 +81,9 @@ 
 #define MMI_LDC1(fp, addr, bias)                                            \
     "ldc1       "#fp",      "#bias"("#addr")                        \n\t"
 
-#define MMI_ULDC1(fp, addr, bias)                                           \
-    "uld        %[all64],   "#bias"("#addr")                        \n\t"   \
+#define MMI_LDLRC1(fp, addr, bias, off)                                     \
+    "ldl        %[all64],   "#bias"+"#off"("#addr")                 \n\t"   \
+    "ldr        %[all64],   "#bias"("#addr")                        \n\t"   \
     "dmtc1      %[all64],   "#fp"                                   \n\t"
 
 #define MMI_LDXC1(fp, addr, stride, bias)                                   \
@@ -90,9 +93,10 @@ 
 #define MMI_SDC1(fp, addr, bias)                                            \
     "sdc1       "#fp",      "#bias"("#addr")                        \n\t"
 
-#define MMI_USDC1(fp, addr, bias)                                           \
+#define MMI_SDLRC1(fp, addr, bias, off)                                           \
     "dmfc1      %[all64],   "#fp"                                   \n\t"   \
-    "usd        %[all64],   "#bias"("#addr")                        \n\t"
+    "sdl        %[all64],   "#bias"+"#off"("#addr")                 \n\t"   \
+    "sdr        %[all64],   "#bias"("#addr")                        \n\t"
 
 #define MMI_SDXC1(fp, addr, stride, bias)                                   \
     PTR_ADDU    "%[addrt],  "#addr",    "#stride"                   \n\t"   \
@@ -141,17 +145,18 @@ 
 #define DECLARE_VAR_LOW32       int32_t low32
 #define RESTRICT_ASM_LOW32      [low32]"=&r"(low32),
 
-#define MMI_ULWC1(fp, addr, bias)                                           \
-    "ulw        %[low32],   "#bias"("#addr")                        \n\t"   \
-    "mtc1       %[low32],   "#fp"                                   \n\t"
+#define MMI_LWLRC1(fp, addr, bias, off)                                     \
+    "lwl        %[low32],   "#bias"+"#off"("#addr")                 \n\t"   \
+    "lwr        %[low32],   "#bias"("#addr")                        \n\t"   \
+    "mtc1       %[low32],   "#fp"                                      \n\t"
 
 #else /* _MIPS_SIM != _ABIO32 */
 
 #define DECLARE_VAR_LOW32
 #define RESTRICT_ASM_LOW32
 
-#define MMI_ULWC1(fp, addr, bias)                                           \
-    "gslwlc1    "#fp",    3+"#bias"("#addr")                        \n\t"   \
+#define MMI_LWLRC1(fp, addr, bias, off)                                     \
+    "gslwlc1    "#fp",      "#off"+"#bias"("#addr")                 \n\t"   \
     "gslwrc1    "#fp",      "#bias"("#addr")                        \n\t"
 
 #endif /* _MIPS_SIM != _ABIO32 */
@@ -162,8 +167,8 @@ 
 #define MMI_SWC1(fp, addr, bias)                                            \
     "swc1       "#fp",      "#bias"("#addr")                        \n\t"
 
-#define MMI_USWC1(fp, addr, bias)                                           \
-    "gsswlc1    "#fp",    3+"#bias"("#addr")                        \n\t"   \
+#define MMI_SWLRC1(fp, addr, bias, off)                                     \
+    "gsswlc1    "#fp",      "#off"+"#bias"("#addr")                 \n\t"   \
     "gsswrc1    "#fp",      "#bias"("#addr")                        \n\t"
 
 #define MMI_SWXC1(fp, addr, stride, bias)                                   \
@@ -172,8 +177,8 @@ 
 #define MMI_LDC1(fp, addr, bias)                                            \
     "ldc1       "#fp",      "#bias"("#addr")                        \n\t"
 
-#define MMI_ULDC1(fp, addr, bias)                                           \
-    "gsldlc1    "#fp",    7+"#bias"("#addr")                        \n\t"   \
+#define MMI_LDLRC1(fp, addr, bias, off)                                     \
+    "gsldlc1    "#fp",      "#off"+"#bias"("#addr")                 \n\t"   \
     "gsldrc1    "#fp",      "#bias"("#addr")                        \n\t"
 
 #define MMI_LDXC1(fp, addr, stride, bias)                                   \
@@ -182,8 +187,8 @@ 
 #define MMI_SDC1(fp, addr, bias)                                            \
     "sdc1       "#fp",      "#bias"("#addr")                        \n\t"
 
-#define MMI_USDC1(fp, addr, bias)                                           \
-    "gssdlc1    "#fp",    7+"#bias"("#addr")                        \n\t"   \
+#define MMI_SDLRC1(fp, addr, bias, off)                                           \
+    "gssdlc1    "#fp",      "#off"+"#bias"("#addr")                 \n\t"   \
     "gssdrc1    "#fp",      "#bias"("#addr")                        \n\t"
 
 #define MMI_SDXC1(fp, addr, stride, bias)                                   \
@@ -203,6 +208,12 @@ 
 
 #endif /* HAVE_LOONGSON2 */
 
+#define MMI_ULWC1(fp, addr, bias) MMI_LWLRC1(fp, addr, bias, 3)
+#define MMI_USWC1(fp, addr, bias) MMI_SWLRC1(fp, addr, bias, 3)
+
+#define MMI_ULDC1(fp, addr, bias) MMI_LDLRC1(fp, addr, bias, 7)
+#define MMI_USDC1(fp, addr, bias) MMI_SDLRC1(fp, addr, bias, 7)
+
 /**
  * Backup saved registers
  * We're not using compiler's clobber list as it's not smart enough