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[79.124.17.100]) by mx.google.com with ESMTP id m19si20989393ejn.748.2021.07.21.03.51.28; Wed, 21 Jul 2021 03:51:28 -0700 (PDT) Received-SPF: pass (google.com: domain of ffmpeg-devel-bounces@ffmpeg.org designates 79.124.17.100 as permitted sender) client-ip=79.124.17.100; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@flygoat.com header.s=fm2 header.b=eSHeXvJa; dkim=neutral (body hash did not verify) header.i=@messagingengine.com header.s=fm3 header.b=S8uYoe72; spf=pass (google.com: domain of ffmpeg-devel-bounces@ffmpeg.org designates 79.124.17.100 as permitted sender) smtp.mailfrom=ffmpeg-devel-bounces@ffmpeg.org Received: from [127.0.1.1] (localhost [127.0.0.1]) by ffbox0-bg.mplayerhq.hu (Postfix) with ESMTP id 22DED68A6E0; Wed, 21 Jul 2021 13:51:08 +0300 (EEST) X-Original-To: ffmpeg-devel@ffmpeg.org Delivered-To: ffmpeg-devel@ffmpeg.org Received: from out1-smtp.messagingengine.com (out1-smtp.messagingengine.com [66.111.4.25]) by ffbox0-bg.mplayerhq.hu (Postfix) with ESMTPS id 3E8B968A305 for ; Wed, 21 Jul 2021 13:50:57 +0300 (EEST) Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.nyi.internal (Postfix) with ESMTP id D8A085C01E2; Wed, 21 Jul 2021 05:19:44 -0400 (EDT) Received: from mailfrontend2 ([10.202.2.163]) by compute4.internal (MEProxy); Wed, 21 Jul 2021 05:19:44 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=flygoat.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; s=fm2; bh=8IYRtKt7jloX6 4sx2gGCT/rrvxUhHwFEFFsSbMA3tFY=; b=eSHeXvJamwTGnYVF8mcDIX9dOESYG 1v1+INo/xsilqd1AD/6yxiPuYskVuuxAjsVFTsGkoh1uOpPwraeVyGQuWQUAUkG9 svXrQRLVXf2QGnGDtQzFxerHxVPIVq4iX52ZVi48EpKbMDxBifr3f07lQ/5l0JXF XhLSOXbegVOpxP/GLmfvbUhX0BOzaoykWwT6gELuc6rUC3Wc1AhoNdmao5nKBQ+w FN02BJOHHnuKRhc0aenBG5S15TVlcpLof1nkmAWVFzdh82ynw+GmmtmTWSkiTouA g/oIB1MgV0tdQHflzIJShAz44RKUmC+GADSgPCDFDP+7PHhnj7JZkBqHA== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:content-transfer-encoding:date:from :in-reply-to:message-id:mime-version:references:subject:to :x-me-proxy:x-me-proxy:x-me-sender:x-me-sender:x-sasl-enc; s= fm3; bh=8IYRtKt7jloX64sx2gGCT/rrvxUhHwFEFFsSbMA3tFY=; b=S8uYoe72 +Qg60KM47vLbv48z3DVn5kAZM2s/9ubnyWgLukupWmxZMioRyVjBCc8PjdFhEMs4 j02lYl9MpX8QgT8uJde+QEe+MHCVchemVt4zXNQAiIPp3xrb1kdfMAYnpHxaTW/i dqo8AssVreoi5+f3Y6wg05PlYxG5apFRIm05sLbjJOPxL2+10T889r7rsSuxig6w JGkVzUPpBpt8fP7aDx1ccMv22Zw/Zuw/8H+9qo3qd5nyFN0Zp3zPuVjQL1D3EuUy MbtGDzpQHH3lIR/WqpRQb2tQz49Z4JpbxvIo2x8UOM/dLDnqzosGeCTDs28V8kru aPRv+42LaYtqTg== X-ME-Sender: X-ME-Received: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedvtddrfeeggddufecutefuodetggdotefrodftvf curfhrohhfihhlvgemucfhrghsthforghilhdpqfgfvfdpuffrtefokffrpgfnqfghnecu uegrihhlohhuthemuceftddtnecunecujfgurhephffvufffkffojghfggfgsedtkeertd ertddtnecuhfhrohhmpeflihgrgihunhcujggrnhhguceojhhirgiguhhnrdihrghnghes fhhlhihgohgrthdrtghomheqnecuggftrfgrthhtvghrnhepjeeihffgteelkeelffduke dtheevudejvdegkeekjeefhffhhfetudetgfdtffeunecuvehluhhsthgvrhfuihiivgep udenucfrrghrrghmpehmrghilhhfrhhomhepjhhirgiguhhnrdihrghnghesfhhlhihgoh grthdrtghomh X-ME-Proxy: Received: by mail.messagingengine.com (Postfix) with ESMTPA; Wed, 21 Jul 2021 05:19:42 -0400 (EDT) From: Jiaxun Yang To: ffmpeg-devel@ffmpeg.org Date: Wed, 21 Jul 2021 17:19:10 +0800 Message-Id: <20210721091913.35072-3-jiaxun.yang@flygoat.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20210721091913.35072-1-jiaxun.yang@flygoat.com> References: <20210721091913.35072-1-jiaxun.yang@flygoat.com> MIME-Version: 1.0 Subject: [FFmpeg-devel] [PATCH v2 2/5] avutil/mips: Extract load store with shift C1 pair marco X-BeenThere: ffmpeg-devel@ffmpeg.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: FFmpeg development discussions and patches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: FFmpeg development discussions and patches Cc: yinshiyou-hf@loongson.cn, Jiaxun Yang Errors-To: ffmpeg-devel-bounces@ffmpeg.org Sender: "ffmpeg-devel" X-TUID: 559H601zYPlX We're doing some fancy hacks with load store with shift C1 beside unaligned load store. Create a marco for l/r pair to allow us use it in these places. Signed-off-by: Jiaxun Yang --- libavutil/mips/mmiutils.h | 49 ++++++++++++++++++++++++--------------- 1 file changed, 30 insertions(+), 19 deletions(-) diff --git a/libavutil/mips/mmiutils.h b/libavutil/mips/mmiutils.h index 41715c6490..f5b600e50c 100644 --- a/libavutil/mips/mmiutils.h +++ b/libavutil/mips/mmiutils.h @@ -57,8 +57,9 @@ #define MMI_LWC1(fp, addr, bias) \ "lwc1 "#fp", "#bias"("#addr") \n\t" -#define MMI_ULWC1(fp, addr, bias) \ - "ulw %[low32], "#bias"("#addr") \n\t" \ +#define MMI_LWLRC1(fp, addr, bias, off) \ + "lwl %[low32], "#bias"+"#off"("#addr") \n\t" \ + "lwr %[low32], "#bias"("#addr") \n\t" \ "mtc1 %[low32], "#fp" \n\t" #define MMI_LWXC1(fp, addr, stride, bias) \ @@ -68,9 +69,10 @@ #define MMI_SWC1(fp, addr, bias) \ "swc1 "#fp", "#bias"("#addr") \n\t" -#define MMI_USWC1(fp, addr, bias) \ +#define MMI_SWLRC1(fp, addr, bias, off) \ "mfc1 %[low32], "#fp" \n\t" \ - "usw %[low32], "#bias"("#addr") \n\t" + "swl %[low32], "#bias"+"#off"("#addr") \n\t" \ + "swr %[low32], "#bias"("#addr") \n\t" #define MMI_SWXC1(fp, addr, stride, bias) \ PTR_ADDU "%[addrt], "#addr", "#stride" \n\t" \ @@ -79,8 +81,9 @@ #define MMI_LDC1(fp, addr, bias) \ "ldc1 "#fp", "#bias"("#addr") \n\t" -#define MMI_ULDC1(fp, addr, bias) \ - "uld %[all64], "#bias"("#addr") \n\t" \ +#define MMI_LDLRC1(fp, addr, bias, off) \ + "ldl %[all64], "#bias"+"#off"("#addr") \n\t" \ + "ldr %[all64], "#bias"("#addr") \n\t" \ "dmtc1 %[all64], "#fp" \n\t" #define MMI_LDXC1(fp, addr, stride, bias) \ @@ -90,9 +93,10 @@ #define MMI_SDC1(fp, addr, bias) \ "sdc1 "#fp", "#bias"("#addr") \n\t" -#define MMI_USDC1(fp, addr, bias) \ +#define MMI_SDLRC1(fp, addr, bias, off) \ "dmfc1 %[all64], "#fp" \n\t" \ - "usd %[all64], "#bias"("#addr") \n\t" + "sdl %[all64], "#bias"+"#off"("#addr") \n\t" \ + "sdr %[all64], "#bias"("#addr") \n\t" #define MMI_SDXC1(fp, addr, stride, bias) \ PTR_ADDU "%[addrt], "#addr", "#stride" \n\t" \ @@ -141,17 +145,18 @@ #define DECLARE_VAR_LOW32 int32_t low32 #define RESTRICT_ASM_LOW32 [low32]"=&r"(low32), -#define MMI_ULWC1(fp, addr, bias) \ - "ulw %[low32], "#bias"("#addr") \n\t" \ - "mtc1 %[low32], "#fp" \n\t" +#define MMI_LWLRC1(fp, addr, bias, off) \ + "lwl %[low32], "#bias"+"#off"("#addr") \n\t" \ + "lwr %[low32], "#bias"("#addr") \n\t" \ + "mtc1 %[low32], "#fp" \n\t" #else /* _MIPS_SIM != _ABIO32 */ #define DECLARE_VAR_LOW32 #define RESTRICT_ASM_LOW32 -#define MMI_ULWC1(fp, addr, bias) \ - "gslwlc1 "#fp", 3+"#bias"("#addr") \n\t" \ +#define MMI_LWLRC1(fp, addr, bias, off) \ + "gslwlc1 "#fp", "#off"+"#bias"("#addr") \n\t" \ "gslwrc1 "#fp", "#bias"("#addr") \n\t" #endif /* _MIPS_SIM != _ABIO32 */ @@ -162,8 +167,8 @@ #define MMI_SWC1(fp, addr, bias) \ "swc1 "#fp", "#bias"("#addr") \n\t" -#define MMI_USWC1(fp, addr, bias) \ - "gsswlc1 "#fp", 3+"#bias"("#addr") \n\t" \ +#define MMI_SWLRC1(fp, addr, bias, off) \ + "gsswlc1 "#fp", "#off"+"#bias"("#addr") \n\t" \ "gsswrc1 "#fp", "#bias"("#addr") \n\t" #define MMI_SWXC1(fp, addr, stride, bias) \ @@ -172,8 +177,8 @@ #define MMI_LDC1(fp, addr, bias) \ "ldc1 "#fp", "#bias"("#addr") \n\t" -#define MMI_ULDC1(fp, addr, bias) \ - "gsldlc1 "#fp", 7+"#bias"("#addr") \n\t" \ +#define MMI_LDLRC1(fp, addr, bias, off) \ + "gsldlc1 "#fp", "#off"+"#bias"("#addr") \n\t" \ "gsldrc1 "#fp", "#bias"("#addr") \n\t" #define MMI_LDXC1(fp, addr, stride, bias) \ @@ -182,8 +187,8 @@ #define MMI_SDC1(fp, addr, bias) \ "sdc1 "#fp", "#bias"("#addr") \n\t" -#define MMI_USDC1(fp, addr, bias) \ - "gssdlc1 "#fp", 7+"#bias"("#addr") \n\t" \ +#define MMI_SDLRC1(fp, addr, bias, off) \ + "gssdlc1 "#fp", "#off"+"#bias"("#addr") \n\t" \ "gssdrc1 "#fp", "#bias"("#addr") \n\t" #define MMI_SDXC1(fp, addr, stride, bias) \ @@ -203,6 +208,12 @@ #endif /* HAVE_LOONGSON2 */ +#define MMI_ULWC1(fp, addr, bias) MMI_LWLRC1(fp, addr, bias, 3) +#define MMI_USWC1(fp, addr, bias) MMI_SWLRC1(fp, addr, bias, 3) + +#define MMI_ULDC1(fp, addr, bias) MMI_LDLRC1(fp, addr, bias, 7) +#define MMI_USDC1(fp, addr, bias) MMI_SDLRC1(fp, addr, bias, 7) + /** * Backup saved registers * We're not using compiler's clobber list as it's not smart enough