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[79.124.17.100]) by mx.google.com with ESMTP id z19si8820710edq.17.2021.07.21.03.52.32; Wed, 21 Jul 2021 03:52:32 -0700 (PDT) Received-SPF: pass (google.com: domain of ffmpeg-devel-bounces@ffmpeg.org designates 79.124.17.100 as permitted sender) client-ip=79.124.17.100; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@flygoat.com header.s=fm2 header.b=Axrmq2P1; dkim=neutral (body hash did not verify) header.i=@messagingengine.com header.s=fm3 header.b=aiRFaI6e; spf=pass (google.com: domain of ffmpeg-devel-bounces@ffmpeg.org designates 79.124.17.100 as permitted sender) smtp.mailfrom=ffmpeg-devel-bounces@ffmpeg.org Received: from [127.0.1.1] (localhost [127.0.0.1]) by ffbox0-bg.mplayerhq.hu (Postfix) with ESMTP id 01D9E68A861; Wed, 21 Jul 2021 13:51:13 +0300 (EEST) X-Original-To: ffmpeg-devel@ffmpeg.org Delivered-To: ffmpeg-devel@ffmpeg.org Received: from out1-smtp.messagingengine.com (out1-smtp.messagingengine.com [66.111.4.25]) by ffbox0-bg.mplayerhq.hu (Postfix) with ESMTPS id 1C16668A447 for ; Wed, 21 Jul 2021 13:51:04 +0300 (EEST) Received: from compute6.internal (compute6.nyi.internal [10.202.2.46]) by mailout.nyi.internal (Postfix) with ESMTP id 8FF7A5C01F6; Wed, 21 Jul 2021 05:19:50 -0400 (EDT) Received: from mailfrontend2 ([10.202.2.163]) by compute6.internal (MEProxy); Wed, 21 Jul 2021 05:19:50 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=flygoat.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; s=fm2; bh=t3RwPfy2L3vEJ Bdn1L0xR09k78NQixPC675GV4aTjmo=; b=Axrmq2P1PFICzVX5a5xVnWFDKuyrX aiyDl4kgauqXbsLPzvnpM5nsiYv6lriw1NIQmT3rr9A6vxn5bwAHLdfFpR6VATPp dXgALolHZgu9FhiXWqalk2j8xxjkZZzCJPhN8xJp87mK3zq/mwvCqigemZXP2Zxw SVs6G/fVJKZHZq7hlLQyUtw2y2Q66yFA7kPXROG2UrRnlmpYuCKZDW0xAJ2s9vwL whoq80fF6wEkObL/nrKCnn5a8975S+Rh13ILFnqj/hxgNIoCxzSsFgfWhEVpoWwB hiQhgI9og6K9GUux1ZJOSJmj7/n1yNhC8mJDbwSOgMmp3nAKrbYMJA3fQ== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:content-transfer-encoding:date:from :in-reply-to:message-id:mime-version:references:subject:to :x-me-proxy:x-me-proxy:x-me-sender:x-me-sender:x-sasl-enc; s= fm3; bh=t3RwPfy2L3vEJBdn1L0xR09k78NQixPC675GV4aTjmo=; b=aiRFaI6e sWQTvOuAew07VGKw3MDsDKy42pehbTBwSBzp8syqIS+nhAVXSoxFmIOmGV4ZB1Ca nDUEry/6cxBPX3eL6cstuifJ6QeTUwYFrm72lcNSKu5EjW71TBLegQ6QxVkkpZdn 4e2qBbY+FSOG4BVvFXoyRzFPMul6tT/XwMod7AVQ+Rjf8wr6nZboV5RWY463QBHH kCHiPSBg0X4hSeu375NYlsYj/Z3aNRSXkiv6YAtu5UNnEqzjHHg/ff9++s2xVKNw MKBqLN7eQID7ThqsZEHi3gwZG5rEwKE/M71NVBYTJckbzmaaN1jyPrZRNtcYOGXp E1IXr+JCkS6zjw== X-ME-Sender: X-ME-Received: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedvtddrfeeggddufecutefuodetggdotefrodftvf curfhrohhfihhlvgemucfhrghsthforghilhdpqfgfvfdpuffrtefokffrpgfnqfghnecu uegrihhlohhuthemuceftddtnecunecujfgurhephffvufffkffojghfggfgsedtkeertd ertddtnecuhfhrohhmpeflihgrgihunhcujggrnhhguceojhhirgiguhhnrdihrghnghes fhhlhihgohgrthdrtghomheqnecuggftrfgrthhtvghrnhepjeeihffgteelkeelffduke dtheevudejvdegkeekjeefhffhhfetudetgfdtffeunecuvehluhhsthgvrhfuihiivgep tdenucfrrghrrghmpehmrghilhhfrhhomhepjhhirgiguhhnrdihrghnghesfhhlhihgoh grthdrtghomh X-ME-Proxy: Received: by mail.messagingengine.com (Postfix) with ESMTPA; Wed, 21 Jul 2021 05:19:48 -0400 (EDT) From: Jiaxun Yang To: ffmpeg-devel@ffmpeg.org Date: Wed, 21 Jul 2021 17:19:12 +0800 Message-Id: <20210721091913.35072-5-jiaxun.yang@flygoat.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20210721091913.35072-1-jiaxun.yang@flygoat.com> References: <20210721091913.35072-1-jiaxun.yang@flygoat.com> MIME-Version: 1.0 Subject: [FFmpeg-devel] [PATCH v2 4/5] avutil/mips: Use $at as MMI macro temporary register X-BeenThere: ffmpeg-devel@ffmpeg.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: FFmpeg development discussions and patches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: FFmpeg development discussions and patches Cc: yinshiyou-hf@loongson.cn, Jiaxun Yang Errors-To: ffmpeg-devel-bounces@ffmpeg.org Sender: "ffmpeg-devel" X-TUID: 60K4Fv8JgZP5 Some function had exceed 30 inline assembly register oprands limiation when using LOONGSON2 version of MMI macros. We can avoid that by take $at, which is register reserved for assembler, as temporary register. As none of instructions used in these macros is pseudo, it is safe to utilize $at here. Signed-off-by: Jiaxun Yang --- libavutil/mips/mmiutils.h | 115 +++++++++++++++++++++++--------------- 1 file changed, 69 insertions(+), 46 deletions(-) diff --git a/libavutil/mips/mmiutils.h b/libavutil/mips/mmiutils.h index f5b600e50c..c1a8046798 100644 --- a/libavutil/mips/mmiutils.h +++ b/libavutil/mips/mmiutils.h @@ -29,78 +29,107 @@ #include "libavutil/mem_internal.h" #include "libavutil/mips/asmdefs.h" -#if HAVE_LOONGSON2 +/* + * These were used to define temporary registers for MMI marcos + * however now we're using $at. They're theoretically unnecessary + * but just leave them here to avoid mess. + */ +#define DECLARE_VAR_LOW32 +#define RESTRICT_ASM_LOW32 +#define DECLARE_VAR_ALL64 +#define RESTRICT_ASM_ALL64 +#define DECLARE_VAR_ADDRT +#define RESTRICT_ASM_ADDRT -#define DECLARE_VAR_LOW32 int32_t low32 -#define RESTRICT_ASM_LOW32 [low32]"=&r"(low32), -#define DECLARE_VAR_ALL64 int64_t all64 -#define RESTRICT_ASM_ALL64 [all64]"=&r"(all64), -#define DECLARE_VAR_ADDRT mips_reg addrt -#define RESTRICT_ASM_ADDRT [addrt]"=&r"(addrt), +#if HAVE_LOONGSON2 #define MMI_LWX(reg, addr, stride, bias) \ - PTR_ADDU "%[addrt], "#addr", "#stride" \n\t" \ - "lw "#reg", "#bias"(%[addrt]) \n\t" + ".set noat \n\t" \ + PTR_ADDU "$at, "#addr", "#stride" \n\t" \ + "lw "#reg", "#bias"($at) \n\t" \ + ".set at \n\t" #define MMI_SWX(reg, addr, stride, bias) \ - PTR_ADDU "%[addrt], "#addr", "#stride" \n\t" \ - "sw "#reg", "#bias"(%[addrt]) \n\t" + ".set noat \n\t" \ + PTR_ADDU "$at, "#addr", "#stride" \n\t" \ + "sw "#reg", "#bias"($at) \n\t" \ + ".set at \n\t" #define MMI_LDX(reg, addr, stride, bias) \ - PTR_ADDU "%[addrt], "#addr", "#stride" \n\t" \ - "ld "#reg", "#bias"(%[addrt]) \n\t" + ".set noat \n\t" \ + PTR_ADDU "$at, "#addr", "#stride" \n\t" \ + "ld "#reg", "#bias"($at) \n\t" \ + ".set at \n\t" #define MMI_SDX(reg, addr, stride, bias) \ - PTR_ADDU "%[addrt], "#addr", "#stride" \n\t" \ - "sd "#reg", "#bias"(%[addrt]) \n\t" + ".set noat \n\t" \ + PTR_ADDU "$at, "#addr", "#stride" \n\t" \ + "sd "#reg", "#bias"($at) \n\t" \ + ".set at \n\t" #define MMI_LWC1(fp, addr, bias) \ "lwc1 "#fp", "#bias"("#addr") \n\t" #define MMI_LWLRC1(fp, addr, bias, off) \ - "lwl %[low32], "#bias"+"#off"("#addr") \n\t" \ - "lwr %[low32], "#bias"("#addr") \n\t" \ - "mtc1 %[low32], "#fp" \n\t" + ".set noat \n\t" \ + "lwl $at, "#bias"+"#off"("#addr") \n\t" \ + "lwr $at, "#bias"("#addr") \n\t" \ + "mtc1 $at, "#fp" \n\t" \ + ".set at \n\t" #define MMI_LWXC1(fp, addr, stride, bias) \ - PTR_ADDU "%[addrt], "#addr", "#stride" \n\t" \ - MMI_LWC1(fp, %[addrt], bias) + ".set noat \n\t" \ + PTR_ADDU "$at, "#addr", "#stride" \n\t" \ + MMI_LWC1(fp, $at, bias) \ + ".set at \n\t" #define MMI_SWC1(fp, addr, bias) \ "swc1 "#fp", "#bias"("#addr") \n\t" #define MMI_SWLRC1(fp, addr, bias, off) \ - "mfc1 %[low32], "#fp" \n\t" \ - "swl %[low32], "#bias"+"#off"("#addr") \n\t" \ - "swr %[low32], "#bias"("#addr") \n\t" + ".set noat \n\t" \ + "mfc1 $at, "#fp" \n\t" \ + "swl $at, "#bias"+"#off"("#addr") \n\t" \ + "swr $at, "#bias"("#addr") \n\t" \ + ".set at \n\t" #define MMI_SWXC1(fp, addr, stride, bias) \ - PTR_ADDU "%[addrt], "#addr", "#stride" \n\t" \ - MMI_SWC1(fp, %[addrt], bias) + ".set noat \n\t" \ + PTR_ADDU "$at, "#addr", "#stride" \n\t" \ + MMI_SWC1(fp, $at, bias) \ + ".set at \n\t" #define MMI_LDC1(fp, addr, bias) \ "ldc1 "#fp", "#bias"("#addr") \n\t" #define MMI_LDLRC1(fp, addr, bias, off) \ - "ldl %[all64], "#bias"+"#off"("#addr") \n\t" \ - "ldr %[all64], "#bias"("#addr") \n\t" \ - "dmtc1 %[all64], "#fp" \n\t" + ".set noat \n\t" \ + "ldl $at, "#bias"+"#off"("#addr") \n\t" \ + "ldr $at, "#bias"("#addr") \n\t" \ + "dmtc1 $at, "#fp" \n\t" \ + ".set at \n\t" #define MMI_LDXC1(fp, addr, stride, bias) \ - PTR_ADDU "%[addrt], "#addr", "#stride" \n\t" \ - MMI_LDC1(fp, %[addrt], bias) + ".set noat \n\t" \ + PTR_ADDU "$at, "#addr", "#stride" \n\t" \ + MMI_LDC1(fp, $at, bias) \ + ".set at \n\t" #define MMI_SDC1(fp, addr, bias) \ "sdc1 "#fp", "#bias"("#addr") \n\t" #define MMI_SDLRC1(fp, addr, bias, off) \ - "dmfc1 %[all64], "#fp" \n\t" \ - "sdl %[all64], "#bias"+"#off"("#addr") \n\t" \ - "sdr %[all64], "#bias"("#addr") \n\t" + ".set noat \n\t" \ + "dmfc1 $at, "#fp" \n\t" \ + "sdl $at, "#bias"+"#off"("#addr") \n\t" \ + "sdr $at, "#bias"("#addr") \n\t" \ + ".set at \n\t" #define MMI_SDXC1(fp, addr, stride, bias) \ - PTR_ADDU "%[addrt], "#addr", "#stride" \n\t" \ - MMI_SDC1(fp, %[addrt], bias) + ".set noat \n\t" \ + PTR_ADDU "$at, "#addr", "#stride" \n\t" \ + MMI_SDC1(fp, $at, bias) \ + ".set at \n\t" #define MMI_LQ(reg1, reg2, addr, bias) \ "ld "#reg1", "#bias"("#addr") \n\t" \ @@ -120,11 +149,6 @@ #elif HAVE_LOONGSON3 /* !HAVE_LOONGSON2 */ -#define DECLARE_VAR_ALL64 -#define RESTRICT_ASM_ALL64 -#define DECLARE_VAR_ADDRT -#define RESTRICT_ASM_ADDRT - #define MMI_LWX(reg, addr, stride, bias) \ "gslwx "#reg", "#bias"("#addr", "#stride") \n\t" @@ -142,13 +166,12 @@ #if _MIPS_SIM == _ABIO32 /* workaround for 3A2000 gslwlc1 bug */ -#define DECLARE_VAR_LOW32 int32_t low32 -#define RESTRICT_ASM_LOW32 [low32]"=&r"(low32), - #define MMI_LWLRC1(fp, addr, bias, off) \ - "lwl %[low32], "#bias"+"#off"("#addr") \n\t" \ - "lwr %[low32], "#bias"("#addr") \n\t" \ - "mtc1 %[low32], "#fp" \n\t" + ".set noat \n\t" \ + "lwl $at, "#bias"+"#off"("#addr") \n\t" \ + "lwr $at, "#bias"("#addr") \n\t" \ + "mtc1 $at, "#fp" \n\t" \ + ".set at \n\t" #else /* _MIPS_SIM != _ABIO32 */