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[FFmpeg-devel,02/18] lavu/riscv: AV_READ_TIME cycle counter

Message ID 20220912155333.59843-2-remi@remlab.net
State New
Headers show
Series [FFmpeg-devel,01/18] doc: reference the RISC-V specification | expand

Checks

Context Check Description
andriy/make_x86 success Make finished
andriy/make_fate_x86 success Make fate finished

Commit Message

Rémi Denis-Courmont Sept. 12, 2022, 3:53 p.m. UTC 
From: Rémi Denis-Courmont <remi@remlab.net>

This uses the architected RISC-V 64-bit cycle counter from the
RISC-V unprivileged instruction set.

In 64-bit and 128-bit, this is a straightforward CSR read.
In 32-bit mode, the 64-bit value is exposed as two CSRs, which
cannot be read atomically, so a loop is necessary to detect and fix up
the race condition where the bottom half wraps exactly between the two
reads.
---
 libavutil/riscv/timer.h | 53 +++++++++++++++++++++++++++++++++++++++++
 libavutil/timer.h       |  2 ++
 2 files changed, 55 insertions(+)
 create mode 100644 libavutil/riscv/timer.h
diff mbox series

Patch

diff --git a/libavutil/riscv/timer.h b/libavutil/riscv/timer.h
new file mode 100644
index 0000000000..a34157a566
--- /dev/null
+++ b/libavutil/riscv/timer.h
@@ -0,0 +1,53 @@ 
+/*
+ * This file is part of FFmpeg.
+ *
+ * FFmpeg is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2.1 of the License, or (at your option) any later version.
+ *
+ * FFmpeg is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with FFmpeg; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef AVUTIL_RISCV_TIMER_H
+#define AVUTIL_RISCV_TIMER_H
+
+#include "config.h"
+
+#if HAVE_INLINE_ASM
+#include <stdint.h>
+
+static inline uint64_t rdcycle64(void)
+{
+#if (__riscv_xlen >= 64)
+    uintptr_t cycles;
+
+    __asm__ volatile ("rdcycle %0" : "=r"(cycles));
+
+#else
+    uint64_t cycles;
+    uint32_t hi, lo, check;
+
+    __asm__ volatile (
+        "1: rdcycleh %0\n"
+        "   rdcycle  %1\n"
+        "   rdcycleh %2\n"
+        "   bne %0, %2, 1b\n" : "=r" (hi), "=r" (lo), "=r" (check));
+
+    cycles = (((uint64_t)hi) << 32) | lo;
+
+#endif
+    return cycles;
+}
+
+#define AV_READ_TIME rdcycle64
+
+#endif
+#endif /* AVUTIL_RISCV_TIMER_H */
diff --git a/libavutil/timer.h b/libavutil/timer.h
index 48e576739f..d3db5a27ef 100644
--- a/libavutil/timer.h
+++ b/libavutil/timer.h
@@ -57,6 +57,8 @@ 
 #   include "arm/timer.h"
 #elif ARCH_PPC
 #   include "ppc/timer.h"
+#elif ARCH_RISCV
+#   include "riscv/timer.h"
 #elif ARCH_X86
 #   include "x86/timer.h"
 #endif