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[FFmpeg-devel,11/26] lavu/floatdsp: RISC-V V vector_fmac_scalar

Message ID 20220920144013.4959-11-remi@remlab.net
State New
Headers show
Series [FFmpeg-devel,01/26] lavu/cpu: detect RISC-V base extensions | expand

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Context Check Description
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yinshiyou/make_fate_loongarch64 success Make fate finished
andriy/make_x86 success Make finished
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Commit Message

Rémi Denis-Courmont Sept. 20, 2022, 2:39 p.m. UTC
From: Rémi Denis-Courmont <remi@remlab.net>

---
 libavutil/riscv/float_dsp_init.c |  3 +++
 libavutil/riscv/float_dsp_rvv.S  | 19 +++++++++++++++++++
 2 files changed, 22 insertions(+)
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Patch

diff --git a/libavutil/riscv/float_dsp_init.c b/libavutil/riscv/float_dsp_init.c
index 6027a67b46..c2d93e0cd7 100644
--- a/libavutil/riscv/float_dsp_init.c
+++ b/libavutil/riscv/float_dsp_init.c
@@ -27,6 +27,8 @@ 
 
 void ff_vector_fmul_rvv(float *dst, const float *src0, const float *src1,
                          int len);
+void ff_vector_fmac_scalar_rvv(float *dst, const float *src, float mul,
+                                int len);
 void ff_vector_fmul_scalar_rvv(float *dst, const float *src, float mul,
                                 int len);
 
@@ -42,6 +44,7 @@  av_cold void ff_float_dsp_init_riscv(AVFloatDSPContext *fdsp)
 
     if (flags & AV_CPU_FLAG_RV_ZVE32F) {
         fdsp->vector_fmul = ff_vector_fmul_rvv;
+        fdsp->vector_fmac_scalar = ff_vector_fmac_scalar_rvv;
         fdsp->vector_fmul_scalar = ff_vector_fmul_scalar_rvv;
 
         if (flags & AV_CPU_FLAG_RV_ZVE64D) {
diff --git a/libavutil/riscv/float_dsp_rvv.S b/libavutil/riscv/float_dsp_rvv.S
index b16c0f3005..1c1fa906e6 100644
--- a/libavutil/riscv/float_dsp_rvv.S
+++ b/libavutil/riscv/float_dsp_rvv.S
@@ -39,6 +39,25 @@  func ff_vector_fmul_rvv, zve32f
         ret
 endfunc
 
+// (a0) += (a1) * fa0 [0..a2-1]
+func ff_vector_fmac_scalar_rvv, zve32f
+NOHWF   fmv.w.x   fa0, a2
+NOHWF   mv        a2, a3
+1:
+        vsetvli   t0, a2, e32, m1, ta, ma
+        slli      t1, t0, 2
+        vle32.v   v24, (a1)
+        add       a1, a1, t1
+        vle32.v   v16, (a0)
+        vfmacc.vf v16, fa0, v24
+        sub       a2, a2, t0
+        vse32.v   v16, (a0)
+        add       a0, a0, t1
+        bnez      a2, 1b
+
+        ret
+endfunc
+
 // (a0) = (a1) * fa0 [0..a2-1]
 func ff_vector_fmul_scalar_rvv, zve32f
 NOHWF   fmv.w.x  fa0, a2