diff mbox series

[FFmpeg-devel,10/29] lavu/floatdsp: RISC-V V vector_dmul

Message ID 20220922183726.38624-10-remi@remlab.net
State New
Headers show
Series [FFmpeg-devel,01/29] lavu/cpu: detect RISC-V base extensions | expand

Checks

Context Check Description
andriy/make_x86 success Make finished
andriy/make_fate_x86 success Make fate finished

Commit Message

Rémi Denis-Courmont Sept. 22, 2022, 6:37 p.m. UTC 
From: Rémi Denis-Courmont <remi@remlab.net>

---
 libavutil/riscv/float_dsp_init.c |  6 +++++-
 libavutil/riscv/float_dsp_rvv.S  | 18 ++++++++++++++++++
 2 files changed, 23 insertions(+), 1 deletion(-)
diff mbox series

Patch

diff --git a/libavutil/riscv/float_dsp_init.c b/libavutil/riscv/float_dsp_init.c
index 60b79bd59e..6027a67b46 100644
--- a/libavutil/riscv/float_dsp_init.c
+++ b/libavutil/riscv/float_dsp_init.c
@@ -30,6 +30,8 @@  void ff_vector_fmul_rvv(float *dst, const float *src0, const float *src1,
 void ff_vector_fmul_scalar_rvv(float *dst, const float *src, float mul,
                                 int len);
 
+void ff_vector_dmul_rvv(double *dst, const double *src0, const double *src1,
+                         int len);
 void ff_vector_dmul_scalar_rvv(double *dst, const double *src, double mul,
                                 int len);
 
@@ -42,8 +44,10 @@  av_cold void ff_float_dsp_init_riscv(AVFloatDSPContext *fdsp)
         fdsp->vector_fmul = ff_vector_fmul_rvv;
         fdsp->vector_fmul_scalar = ff_vector_fmul_scalar_rvv;
 
-        if (flags & AV_CPU_FLAG_RV_ZVE64D)
+        if (flags & AV_CPU_FLAG_RV_ZVE64D) {
+            fdsp->vector_dmul = ff_vector_dmul_rvv;
             fdsp->vector_dmul_scalar = ff_vector_dmul_scalar_rvv;
+        }
     }
 #endif
 }
diff --git a/libavutil/riscv/float_dsp_rvv.S b/libavutil/riscv/float_dsp_rvv.S
index fb2cb54081..b16c0f3005 100644
--- a/libavutil/riscv/float_dsp_rvv.S
+++ b/libavutil/riscv/float_dsp_rvv.S
@@ -57,6 +57,24 @@  NOHWF   mv       a2, a3
         ret
 endfunc
 
+// (a0) = (a1) * (a2) [0..a3-1]
+func ff_vector_dmul_rvv, zve64d
+1:
+        vsetvli  t0, a3, e64, m1, ta, ma
+        slli     t1, t0, 3
+        vle64.v  v16, (a1)
+        add      a1, a1, t1
+        vle64.v  v24, (a2)
+        add      a2, a2, t1
+        vfmul.vv v16, v16, v24
+        sub      a3, a3, t0
+        vse64.v  v16, (a0)
+        add      a0, a0, t1
+        bnez     a3, 1b
+
+        ret
+endfunc
+
 // (a0) = (a1) * fa0 [0..a2-1]
 func ff_vector_dmul_scalar_rvv, zve64d
 NOHWD   fmv.d.x  fa0, a2