From patchwork Sun Sep 25 14:26:19 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?R=C3=A9mi_Denis-Courmont?= X-Patchwork-Id: 38284 Delivered-To: ffmpegpatchwork2@gmail.com Received: by 2002:a05:6a20:3b1c:b0:96:9ee8:5cfd with SMTP id c28csp1707920pzh; Sun, 25 Sep 2022 07:30:52 -0700 (PDT) X-Google-Smtp-Source: AMsMyM5qb/mCuug//W4bKa+3zGMUvI0rk1XjUK0uy6erPpeGvIcRCmVBpmVk7xbYlob2D53awiRX X-Received: by 2002:a17:907:9804:b0:77f:364f:b797 with SMTP id ji4-20020a170907980400b0077f364fb797mr14583363ejc.88.1664116252021; Sun, 25 Sep 2022 07:30:52 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1664116252; cv=none; d=google.com; s=arc-20160816; b=RoYXJrwNMo8D2eXv9K6ydHJnEfO2KUE41DYgIwhItJXOXcqIZ3MqC4O3DujoG0BDIE 4H26m8K8RXjUSYKLAXZHpP50d6FIe/gNDVsLe9a0bGY9BJNpbJQUCpMbdVMcD/ZMe+zL ajWxXJb4Vdl9PaXLwPB/b3Y1OeHpb5xBrPL+pVmkW6E1pckWCdI969zYv3i1LbVXGOsj Cei3ZS4O8U8OieGOEjukESryhYX4i9UqcqVzQtEaFxIQMfUaudoW4zQdDYA3iDW/zLI1 Lfts+/6WtFM77B+nFldxVj9sXvFPQDze3RY9nuxJnPvY8uuhhM66r/nvYd5kEngA/T9H Fmjw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:reply-to:list-subscribe :list-help:list-post:list-archive:list-unsubscribe:list-id :precedence:subject:mime-version:references:in-reply-to:message-id :date:to:from:delivered-to; bh=o0idrz/HTgivVK1ebFMS+IEI8DilaN8sjbr7EqpYaa4=; b=EdJpACA2Mv6PF/xMMqr7+R43fG+Q5uVYviKzKTLl+KZZgb1AFrY52/L1TyVcHZEnL5 0dseIGftNvYFVW8AID/ZvL+dImvSxlJsoeHGOM8Vm0K3tUZ8DwiIS171R0jyP5UvOCWl bPYX9Dzw5FLd6KBjIJMDo34HPjJgnT2SJn/z/4kNpB2Yqhsdv/7sUw2Ygb8yP+Y6RsQ+ +nP+xsgS/oGFuGqehuaoKKpcU1ooTtG8imiR0G4yZ6dgw2XSQ119DsqzhKROhAG5P8sM Lj62VBq4CESnut2mov4/ThMotr40FCOY+2OKL9fM1voMxG9duvJvU6WRTgk5eVvF1jS0 1J6w== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of ffmpeg-devel-bounces@ffmpeg.org designates 79.124.17.100 as permitted sender) smtp.mailfrom=ffmpeg-devel-bounces@ffmpeg.org Return-Path: Received: from ffbox0-bg.mplayerhq.hu (ffbox0-bg.ffmpeg.org. [79.124.17.100]) by mx.google.com with ESMTP id go34-20020a1709070da200b0078034101c0esi13968166ejc.978.2022.09.25.07.30.51; Sun, 25 Sep 2022 07:30:52 -0700 (PDT) Received-SPF: pass (google.com: domain of ffmpeg-devel-bounces@ffmpeg.org designates 79.124.17.100 as permitted sender) client-ip=79.124.17.100; Authentication-Results: mx.google.com; spf=pass (google.com: domain of ffmpeg-devel-bounces@ffmpeg.org designates 79.124.17.100 as permitted sender) smtp.mailfrom=ffmpeg-devel-bounces@ffmpeg.org Received: from [127.0.1.1] (localhost [127.0.0.1]) by ffbox0-bg.mplayerhq.hu (Postfix) with ESMTP id EA31B68BC48; Sun, 25 Sep 2022 17:26:54 +0300 (EEST) X-Original-To: ffmpeg-devel@ffmpeg.org Delivered-To: ffmpeg-devel@ffmpeg.org Received: from ursule.remlab.net (vps-a2bccee9.vps.ovh.net [51.75.19.47]) by ffbox0-bg.mplayerhq.hu (Postfix) with ESMTP id 57F5568BB7F for ; Sun, 25 Sep 2022 17:26:26 +0300 (EEST) Received: from basile.remlab.net (localhost [IPv6:::1]) by ursule.remlab.net (Postfix) with ESMTP id DF1DDC00CB for ; Sun, 25 Sep 2022 17:26:24 +0300 (EEST) From: remi@remlab.net To: ffmpeg-devel@ffmpeg.org Date: Sun, 25 Sep 2022 17:26:19 +0300 Message-Id: <20220925142619.67917-31-remi@remlab.net> X-Mailer: git-send-email 2.37.2 In-Reply-To: <5861881.lOV4Wx5bFT@basile.remlab.net> References: <5861881.lOV4Wx5bFT@basile.remlab.net> MIME-Version: 1.0 Subject: [FFmpeg-devel] [PATCH 31/31] lavc/aacpsdsp: RISC-V V stereo_interpolate[0] X-BeenThere: ffmpeg-devel@ffmpeg.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: FFmpeg development discussions and patches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: FFmpeg development discussions and patches Errors-To: ffmpeg-devel-bounces@ffmpeg.org Sender: "ffmpeg-devel" X-TUID: M/zxmJPvJZuC From: RĂ©mi Denis-Courmont --- libavcodec/riscv/aacpsdsp_init.c | 4 ++ libavcodec/riscv/aacpsdsp_rvv.S | 65 ++++++++++++++++++++++++++++++++ 2 files changed, 69 insertions(+) diff --git a/libavcodec/riscv/aacpsdsp_init.c b/libavcodec/riscv/aacpsdsp_init.c index 20b1a12741..58a4c61121 100644 --- a/libavcodec/riscv/aacpsdsp_init.c +++ b/libavcodec/riscv/aacpsdsp_init.c @@ -34,6 +34,9 @@ void ff_ps_hybrid_analysis_ileave_rvv(float (*out)[32][2], float L[2][38][64], void ff_ps_hybrid_synthesis_deint_rvv(float out[2][38][64], float (*in)[32][2], int i, int len); +void ff_ps_stereo_interpolate_rvv(float (*l)[2], float (*r)[2], + float h[2][4], float h_step[2][4], int len); + av_cold void ff_psdsp_init_riscv(PSDSPContext *c) { #if HAVE_RVV @@ -47,6 +50,7 @@ av_cold void ff_psdsp_init_riscv(PSDSPContext *c) c->add_squares = ff_ps_add_squares_rvv; c->mul_pair_single = ff_ps_mul_pair_single_rvv; c->hybrid_analysis = ff_ps_hybrid_analysis_rvv; + c->stereo_interpolate[0] = ff_ps_stereo_interpolate_rvv; } } #endif diff --git a/libavcodec/riscv/aacpsdsp_rvv.S b/libavcodec/riscv/aacpsdsp_rvv.S index 0cbe4c1d3c..a236dfe43c 100644 --- a/libavcodec/riscv/aacpsdsp_rvv.S +++ b/libavcodec/riscv/aacpsdsp_rvv.S @@ -219,3 +219,68 @@ func ff_ps_hybrid_synthesis_deint_rvv, zve32x 3: ret endfunc + +func ff_ps_stereo_interpolate_rvv, zve32f + vsetvli t0, zero, e32, m1, ta, ma + vid.v v24 + flw ft0, (a2) + vadd.vi v24, v24, 1 // v24[i] = i + 1 + flw ft1, 4(a2) + vfcvt.f.xu.v v24, v24 + flw ft2, 8(a2) + vfmv.v.f v16, ft0 + flw ft3, 12(a2) + vfmv.v.f v17, ft1 + flw ft0, (a3) + vfmv.v.f v18, ft2 + flw ft1, 4(a3) + vfmv.v.f v19, ft3 + flw ft2, 8(a3) + vfmv.v.f v20, ft0 + flw ft3, 12(a3) + vfmv.v.f v21, ft1 + fcvt.s.wu ft4, t0 // (float)(vlenb / sizeof (float)) + vfmv.v.f v22, ft2 + li t1, 8 + vfmv.v.f v23, ft3 + addi a6, a0, 4 // l[*][1] + vfmacc.vv v16, v24, v20 // h0 += (i + 1) * h0_step + addi a7, a1, 4 // r[*][1] + vfmacc.vv v17, v24, v21 + fmul.s ft0, ft0, ft4 + vfmacc.vv v18, v24, v22 + fmul.s ft1, ft1, ft4 + vfmacc.vv v19, v24, v23 + fmul.s ft2, ft2, ft4 + fmul.s ft3, ft3, ft4 +1: + vsetvli t0, a4, e32, m1, ta, ma + vlse32.v v8, (a0), t1 // l_re + sub a4, a4, t0 + vlse32.v v9, (a6), t1 // l_im + vlse32.v v10, (a1), t1 // r_re + vlse32.v v11, (a7), t1 // r_im + vfmul.vv v12, v8, v16 + vfmul.vv v13, v9, v16 + vfmul.vv v14, v8, v17 + vfmul.vv v15, v9, v17 + vfmacc.vv v12, v10, v18 + vfmacc.vv v13, v11, v18 + vfmacc.vv v14, v10, v19 + vfmacc.vv v15, v11, v19 + vsse32.v v12, (a0), t1 + sh3add a0, t0, a0 + vsse32.v v13, (a6), t1 + sh3add a6, t0, a6 + vsse32.v v14, (a1), t1 + sh3add a1, t0, a1 + vsse32.v v15, (a7), t1 + sh3add a7, t0, a7 + vfadd.vf v16, v16, ft0 // h0 += (vlenb / sizeof (float)) * h0_step + vfadd.vf v17, v17, ft1 + vfadd.vf v18, v18, ft2 + vfadd.vf v19, v19, ft3 + bnez a4, 1b + + ret +endfunc