From patchwork Mon Sep 26 14:52:25 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?R=C3=A9mi_Denis-Courmont?= X-Patchwork-Id: 38349 Delivered-To: ffmpegpatchwork2@gmail.com Received: by 2002:a05:6a20:3b1c:b0:96:9ee8:5cfd with SMTP id c28csp2304865pzh; Mon, 26 Sep 2022 07:54:51 -0700 (PDT) X-Google-Smtp-Source: AMsMyM49oqQHh7gMHiSNVesMHLqQUS1EDyc+b3IgwUl+rp/tNdO3ep26BI57/na/tEIhmGyw08fW X-Received: by 2002:a17:907:843:b0:73a:5b0e:8352 with SMTP id ww3-20020a170907084300b0073a5b0e8352mr18903320ejb.438.1664204091340; Mon, 26 Sep 2022 07:54:51 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1664204091; cv=none; d=google.com; s=arc-20160816; b=YQ6deE6khvezI8Ze0nK6b3cSdiNfPyjmsmAOt0V9pYBtdzZoa4jYnYTT3qpYu+SPaH q643Gc59J6wRcXGh92xpHnHeFmgQGoawe6Fxkn6nH8cbYVHFhsbK7/vL72agUyLaurx5 L0xcEKwtGWsTx7BeBT3jZlIyYJOzOYaGoDI1Ux42cYrtHpYrofjvqHGmDoS+nD1twEO5 Go2ysS3CvUuQl6ip4OaMJ2asv6938mRnV50l3VQrDiD1k0B57c9lenJ3P2HshhmUkTle R0WO5hrzGCJnWWcDCmPzREgGNsrzNvBiGIC8cgjE5q6ja0xzZ1+Kq8tKkUM7TGKPe8zo rodg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:reply-to:list-subscribe :list-help:list-post:list-archive:list-unsubscribe:list-id :precedence:subject:mime-version:references:in-reply-to:message-id :date:to:from:delivered-to; bh=d3goI1BLy1jOHpETSNrxuoOw2NDyWRwkfTkVelgkCPc=; b=ClhetCome7ux3rx8zmqXfFg3n4npmj2uBXmU9I3sBiyZBGqrlmvMWZ6Rdb9x1RVzsw BP+06yndPvPpOi6G2a2PlWQiHcclShTIiNwdR18h4V4SMhJ2VSUnGCHDD04fIaIoIVzj VRwTvHwnRsZBqE9v3W7q7lll4TpWs/uHvZtkF1QdmA/kUHbj+ASI+SOI98WJXPK3MXQk m/gQoT3YT4L20vy7ecnswzS5fdS6aPvWuCbAiS6iCHkITFm86FSrHvEJGAyEi+bPfzzK iLx8BGk4CUawU5zgYECAbFXUCwB3NFhfWrAuPpBPheY01AYhtkuQb4hzW4yPxwJ8j8CI 0+1g== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of ffmpeg-devel-bounces@ffmpeg.org designates 79.124.17.100 as permitted sender) smtp.mailfrom=ffmpeg-devel-bounces@ffmpeg.org Return-Path: Received: from ffbox0-bg.mplayerhq.hu (ffbox0-bg.ffmpeg.org. [79.124.17.100]) by mx.google.com with ESMTP id qn5-20020a170907210500b00781d695b597si91481ejb.473.2022.09.26.07.54.51; Mon, 26 Sep 2022 07:54:51 -0700 (PDT) Received-SPF: pass (google.com: domain of ffmpeg-devel-bounces@ffmpeg.org designates 79.124.17.100 as permitted sender) client-ip=79.124.17.100; Authentication-Results: mx.google.com; spf=pass (google.com: domain of ffmpeg-devel-bounces@ffmpeg.org designates 79.124.17.100 as permitted sender) smtp.mailfrom=ffmpeg-devel-bounces@ffmpeg.org Received: from [127.0.1.1] (localhost [127.0.0.1]) by ffbox0-bg.mplayerhq.hu (Postfix) with ESMTP id E472E68BB0A; Mon, 26 Sep 2022 17:53:09 +0300 (EEST) X-Original-To: ffmpeg-devel@ffmpeg.org Delivered-To: ffmpeg-devel@ffmpeg.org Received: from ursule.remlab.net (vps-a2bccee9.vps.ovh.net [51.75.19.47]) by ffbox0-bg.mplayerhq.hu (Postfix) with ESMTP id 459C368BA9C for ; Mon, 26 Sep 2022 17:52:52 +0300 (EEST) Received: from basile.remlab.net (localhost [IPv6:::1]) by ursule.remlab.net (Postfix) with ESMTP id 04175C00B1 for ; Mon, 26 Sep 2022 17:52:51 +0300 (EEST) From: remi@remlab.net To: ffmpeg-devel@ffmpeg.org Date: Mon, 26 Sep 2022 17:52:25 +0300 Message-Id: <20220926145251.56351-5-remi@remlab.net> X-Mailer: git-send-email 2.37.2 In-Reply-To: <5862173.lOV4Wx5bFT@basile.remlab.net> References: <5862173.lOV4Wx5bFT@basile.remlab.net> MIME-Version: 1.0 Subject: [FFmpeg-devel] [PATCH 05/31] lavu/cpu: CPU flags for the RISC-V Vector extension X-BeenThere: ffmpeg-devel@ffmpeg.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: FFmpeg development discussions and patches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: FFmpeg development discussions and patches Errors-To: ffmpeg-devel-bounces@ffmpeg.org Sender: "ffmpeg-devel" X-TUID: Ijx9LG+j0eAG From: RĂ©mi Denis-Courmont RVV defines a total of 12 different extensions, including: - 5 different instruction subsets: - Zve32x: 8-, 16- and 32-bit integers, - Zve32f: Zve32x plus single precision floats, - Zve64x: Zve32x plus 64-bit integers, - Zve64f: Zve32f plus Zve64x, - Zve64d: Zve64f plus double precision floats. - 6 different vector lengths: - Zvl32b (embedded only), - Zvl64b (embedded only), - Zvl128b, - Zvl256b, - Zvl512b, - Zvl1024b, - and the V extension proper: equivalent to Zve64f and Zvl128b. In total, there are 6 different possible sets of supported instructions (including the empty set), but for convenience we allocate one bit for each type sets: up-to-32-bit ints (RVV_I32), floats (RVV_F32), 64-bit ints (RVV_I64) and doubles (RVV_F64). Whence the vector size is needed, it can be retrieved by reading the unprivileged read-only vlenb CSR. This should probably be a separate helper macro if needed at a later point. --- libavutil/cpu.c | 4 ++++ libavutil/cpu.h | 4 ++++ libavutil/riscv/cpu.c | 19 +++++++++++++++++++ tests/checkasm/checkasm.c | 4 ++++ 4 files changed, 31 insertions(+) diff --git a/libavutil/cpu.c b/libavutil/cpu.c index 8b6eef9873..5818fd9c1c 100644 --- a/libavutil/cpu.c +++ b/libavutil/cpu.c @@ -184,6 +184,10 @@ int av_parse_cpu_caps(unsigned *flags, const char *s) { "rvi", NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_RVI }, .unit = "flags" }, { "rvf", NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_RVF }, .unit = "flags" }, { "rvd", NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_RVD }, .unit = "flags" }, + { "rvv-i32", NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_RVV_I32 }, .unit = "flags" }, + { "rvv-f32", NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_RVV_F32 }, .unit = "flags" }, + { "rvv-i64", NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_RVV_I64 }, .unit = "flags" }, + { "rvv", NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_RVV_F64 }, .unit = "flags" }, #endif { NULL }, }; diff --git a/libavutil/cpu.h b/libavutil/cpu.h index 9aae2ccc7a..18f42af015 100644 --- a/libavutil/cpu.h +++ b/libavutil/cpu.h @@ -82,6 +82,10 @@ #define AV_CPU_FLAG_RVI (1 << 0) ///< I (full GPR bank) #define AV_CPU_FLAG_RVF (1 << 1) ///< F (single precision FP) #define AV_CPU_FLAG_RVD (1 << 2) ///< D (double precision FP) +#define AV_CPU_FLAG_RVV_I32 (1 << 3) ///< Vectors of 8/16/32-bit int's */ +#define AV_CPU_FLAG_RVV_F32 (1 << 4) ///< Vectors of float's */ +#define AV_CPU_FLAG_RVV_I64 (1 << 5) ///< Vectors of 64-bit int's */ +#define AV_CPU_FLAG_RVV_F64 (1 << 6) ///< Vectors of double's /** * Return the flags which specify extensions supported by the CPU. diff --git a/libavutil/riscv/cpu.c b/libavutil/riscv/cpu.c index 6803f035e5..e234201395 100644 --- a/libavutil/riscv/cpu.c +++ b/libavutil/riscv/cpu.c @@ -40,6 +40,11 @@ int ff_get_cpu_flags_riscv(void) ret |= AV_CPU_FLAG_RVF; if (hwcap & HWCAP_RV('D')) ret |= AV_CPU_FLAG_RVD; + + /* The V extension implies all Zve* functional subsets */ + if (hwcap & HWCAP_RV('V')) + ret |= AV_CPU_FLAG_RVV_I32 | AV_CPU_FLAG_RVV_I64 + | AV_CPU_FLAG_RVV_F32 | AV_CPU_FLAG_RVV_F64; #endif #ifdef __riscv_i @@ -50,6 +55,20 @@ int ff_get_cpu_flags_riscv(void) #if (__riscv_flen >= 64) ret |= AV_CPU_FLAG_RVD; #endif +#endif + + /* If RV-V is enabled statically at compile-time, check the details. */ +#ifdef __riscv_vectors + ret |= AV_CPU_FLAG_RVV_I32; +#if __riscv_v_elen >= 64 + ret |= AV_CPU_FLAG_RVV_I64; +#endif +#if __riscv_v_elen_fp >= 32 + ret |= AV_CPU_FLAG_RVV_F32; +#if __riscv_v_elen_fp >= 64 + ret |= AV_CPU_FLAG_RVV_F64; +#endif +#endif #endif return ret; diff --git a/tests/checkasm/checkasm.c b/tests/checkasm/checkasm.c index e1135a84ac..90dd7e4634 100644 --- a/tests/checkasm/checkasm.c +++ b/tests/checkasm/checkasm.c @@ -236,6 +236,10 @@ static const struct { { "RVI", "rvi", AV_CPU_FLAG_RVI }, { "RVF", "rvf", AV_CPU_FLAG_RVF }, { "RVD", "rvd", AV_CPU_FLAG_RVD }, + { "RVVi32", "rvv_i32", AV_CPU_FLAG_RVV_I32 }, + { "RVVf32", "rvv_f32", AV_CPU_FLAG_RVV_F32 }, + { "RVVi64", "rvv_i64", AV_CPU_FLAG_RVV_I64 }, + { "RVVf64", "rvv_f64", AV_CPU_FLAG_RVV_F64 }, #elif ARCH_MIPS { "MMI", "mmi", AV_CPU_FLAG_MMI }, { "MSA", "msa", AV_CPU_FLAG_MSA },