From patchwork Sun Oct 2 11:54:58 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?R=C3=A9mi_Denis-Courmont?= X-Patchwork-Id: 38514 Delivered-To: ffmpegpatchwork2@gmail.com Received: by 2002:a05:6a20:3b1c:b0:96:9ee8:5cfd with SMTP id c28csp744910pzh; Sun, 2 Oct 2022 04:55:11 -0700 (PDT) X-Google-Smtp-Source: AMsMyM6b3OHROcozFmTL0uyw2Q7Qa0sSF6sYNVEgVz5BCaqyxO82EPFP8A8G9/rv1buMWnogADGg X-Received: by 2002:a17:907:743:b0:740:ef93:2ffc with SMTP id xc3-20020a170907074300b00740ef932ffcmr12353157ejb.514.1664711710850; Sun, 02 Oct 2022 04:55:10 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1664711710; cv=none; d=google.com; s=arc-20160816; b=BX1eMJluCdoW19MClxC6p69DlE0q+5hajOXmxPXPHARGsdMkdrOSykpqjVC8etfz/V MovwNPk9oUP4Br2L1dNxU7iciGRdlAaY5YE9btaVf8xPO3NvA+9/73NJBIYHNKvZPRau QFgymPwEFXgCxCCtC85WGNYVDxZeJf7WRKXEcTStswWaiso7rJFEonOpFFcVT/GLkMCV 4UuP2r2FHwIW1FI830+9QYiTwgmKxGYf3mL1qvXkC6bm6g/KbKZkKnh3Ri0+qob0Egw2 E4RbzBpoU08iQUeugQgn0eys3DfXUibsnMwqQ7uyEgmEODR0DDZGQR6o26h33OV7vNU3 wdIg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:reply-to:list-subscribe :list-help:list-post:list-archive:list-unsubscribe:list-id :precedence:subject:mime-version:references:in-reply-to:message-id :date:to:from:delivered-to; bh=PpvB/ZiYQuLe6wICYs+xuYrgr/qT3vNbHDrnII3OBvI=; b=b4Crksp+jC+WgRymyr02LS4XfsxiKB9ud01MekkFjBkbbv2Efr0zWgaoGNnvFMhIgJ V3nW79L+U/QypNUDmLfldF3DjWauiCOpkblEbFmFa825G4p0AdgwYiMQ2NQC5B0x68RD 6wMR6Ij//SXy8F297jD7Ws2LZIOkq2FjjNMOYuGXpLXf1z2VBblBlkdKjX2biYwXzwi+ lMbDOMFfVkfr+fFxRYV7WebwAr0EormoE2orX0bwISMoWaQQ5iEalyfppZgWOQJ/Wgnh ryPfj9XXQamY06BQ+v00k10C39fW2j5aLDTwbQ9hvbh8WCrU989QALjQ5iWzAqqC2azM Fm9A== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of ffmpeg-devel-bounces@ffmpeg.org designates 79.124.17.100 as permitted sender) smtp.mailfrom=ffmpeg-devel-bounces@ffmpeg.org Return-Path: Received: from ffbox0-bg.mplayerhq.hu (ffbox0-bg.ffmpeg.org. [79.124.17.100]) by mx.google.com with ESMTP id d7-20020a170906174700b0077fd5b45e18si4391280eje.929.2022.10.02.04.55.10; Sun, 02 Oct 2022 04:55:10 -0700 (PDT) Received-SPF: pass (google.com: domain of ffmpeg-devel-bounces@ffmpeg.org designates 79.124.17.100 as permitted sender) client-ip=79.124.17.100; Authentication-Results: mx.google.com; spf=pass (google.com: domain of ffmpeg-devel-bounces@ffmpeg.org designates 79.124.17.100 as permitted sender) smtp.mailfrom=ffmpeg-devel-bounces@ffmpeg.org Received: from [127.0.1.1] (localhost [127.0.0.1]) by ffbox0-bg.mplayerhq.hu (Postfix) with ESMTP id 504F868BB5D; Sun, 2 Oct 2022 14:55:08 +0300 (EEST) X-Original-To: ffmpeg-devel@ffmpeg.org Delivered-To: ffmpeg-devel@ffmpeg.org Received: from ursule.remlab.net (vps-a2bccee9.vps.ovh.net [51.75.19.47]) by ffbox0-bg.mplayerhq.hu (Postfix) with ESMTP id 0713F68BAFE for ; Sun, 2 Oct 2022 14:55:02 +0300 (EEST) Received: from basile.remlab.net (localhost [IPv6:::1]) by ursule.remlab.net (Postfix) with ESMTP id B4B81C006F for ; Sun, 2 Oct 2022 14:55:01 +0300 (EEST) From: remi@remlab.net To: ffmpeg-devel@ffmpeg.org Date: Sun, 2 Oct 2022 14:54:58 +0300 Message-Id: <20221002115501.17996-1-remi@remlab.net> X-Mailer: git-send-email 2.37.2 In-Reply-To: <2650188.mvXUDI8C0e@basile.remlab.net> References: <2650188.mvXUDI8C0e@basile.remlab.net> MIME-Version: 1.0 Subject: [FFmpeg-devel] [PATCH 1/4] lavu/riscv: CPU flag for the Zbb extension X-BeenThere: ffmpeg-devel@ffmpeg.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: FFmpeg development discussions and patches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: FFmpeg development discussions and patches Errors-To: ffmpeg-devel-bounces@ffmpeg.org Sender: "ffmpeg-devel" X-TUID: 4hzcz6Oja7p/ From: Rémi Denis-Courmont Unfortunately, it is common, and will remain so, that the Bit manipulations are not enabled at compilation time. This is an official policy for Debian ports in general (though they do not support RISC-V officially as of yet) to stick to the minimal target baseline, which does not include the B extension or even its Zbb subset. For inline helpers (CPOP, REV8), compiler builtins (CTZ, CLZ) or even plain C code (MIN, MAX, MINU, MAXU), run-time detection seems impractical. But at least it can work for the byte-swap DSP functions. --- libavutil/cpu.c | 1 + libavutil/cpu.h | 1 + libavutil/riscv/cpu.c | 6 ++++++ tests/checkasm/checkasm.c | 1 + 4 files changed, 9 insertions(+) diff --git a/libavutil/cpu.c b/libavutil/cpu.c index 5818fd9c1c..2c5f7f4958 100644 --- a/libavutil/cpu.c +++ b/libavutil/cpu.c @@ -188,6 +188,7 @@ int av_parse_cpu_caps(unsigned *flags, const char *s) { "rvv-f32", NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_RVV_F32 }, .unit = "flags" }, { "rvv-i64", NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_RVV_I64 }, .unit = "flags" }, { "rvv", NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_RVV_F64 }, .unit = "flags" }, + { "rvb-basic",NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_RVB_BASIC }, .unit = "flags" }, #endif { NULL }, }; diff --git a/libavutil/cpu.h b/libavutil/cpu.h index 18f42af015..8fa5ea9199 100644 --- a/libavutil/cpu.h +++ b/libavutil/cpu.h @@ -86,6 +86,7 @@ #define AV_CPU_FLAG_RVV_F32 (1 << 4) ///< Vectors of float's */ #define AV_CPU_FLAG_RVV_I64 (1 << 5) ///< Vectors of 64-bit int's */ #define AV_CPU_FLAG_RVV_F64 (1 << 6) ///< Vectors of double's +#define AV_CPU_FLAG_RVB_BASIC (1 << 7) ///< Basic bit-manipulations /** * Return the flags which specify extensions supported by the CPU. diff --git a/libavutil/riscv/cpu.c b/libavutil/riscv/cpu.c index e234201395..a9263dbb78 100644 --- a/libavutil/riscv/cpu.c +++ b/libavutil/riscv/cpu.c @@ -40,6 +40,8 @@ int ff_get_cpu_flags_riscv(void) ret |= AV_CPU_FLAG_RVF; if (hwcap & HWCAP_RV('D')) ret |= AV_CPU_FLAG_RVD; + if (hwcap & HWCAP_RV('B')) + ret |= AV_CPU_FLAG_RVB_BASIC; /* The V extension implies all Zve* functional subsets */ if (hwcap & HWCAP_RV('V')) @@ -57,6 +59,10 @@ int ff_get_cpu_flags_riscv(void) #endif #endif +#ifdef __riscv_zbb + ret |= AV_CPU_FLAG_RVB_BASIC; +#endif + /* If RV-V is enabled statically at compile-time, check the details. */ #ifdef __riscv_vectors ret |= AV_CPU_FLAG_RVV_I32; diff --git a/tests/checkasm/checkasm.c b/tests/checkasm/checkasm.c index 90dd7e4634..421bd096c5 100644 --- a/tests/checkasm/checkasm.c +++ b/tests/checkasm/checkasm.c @@ -240,6 +240,7 @@ static const struct { { "RVVf32", "rvv_f32", AV_CPU_FLAG_RVV_F32 }, { "RVVi64", "rvv_i64", AV_CPU_FLAG_RVV_I64 }, { "RVVf64", "rvv_f64", AV_CPU_FLAG_RVV_F64 }, + { "RVBbasic", "rvb_b", AV_CPU_FLAG_RVB_BASIC }, #elif ARCH_MIPS { "MMI", "mmi", AV_CPU_FLAG_MMI }, { "MSA", "msa", AV_CPU_FLAG_MSA },