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[FFmpeg-devel,3/4] lavc/opusdsp: RISC-V V (256-bit) postfilter

Message ID 20221005161256.27612-3-remi@remlab.net
State New
Headers show
Series RISC-V V Opus postfilter | expand


Context Check Description
andriy/make_x86 success Make finished
andriy/make_fate_x86 success Make fate finished

Commit Message

Rémi Denis-Courmont Oct. 5, 2022, 4:12 p.m. UTC
This adds a variant of the postfilter for use with 256-bit vectors.
As a single vector is then large enough to perform the scalar product,
the group multipler is reduced to just one at run-time.

The different vector type is passed via register. Unfortunately,
there is no VSETIVL instruction, so the constant vector size (5) also
needs to be passed via a register.
 libavcodec/riscv/opusdsp_init.c |  4 ++++
 libavcodec/riscv/opusdsp_rvv.S  | 16 ++++++++++++----
 2 files changed, 16 insertions(+), 4 deletions(-)
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diff --git a/libavcodec/riscv/opusdsp_init.c b/libavcodec/riscv/opusdsp_init.c
index f1d2c871e3..e6f9505f77 100644
--- a/libavcodec/riscv/opusdsp_init.c
+++ b/libavcodec/riscv/opusdsp_init.c
@@ -26,6 +26,7 @@ 
 #include "libavcodec/opusdsp.h"
 void ff_opus_postfilter_rvv_128(float *data, int period, float *g, int len);
+void ff_opus_postfilter_rvv_256(float *data, int period, float *g, int len);
 av_cold void ff_opus_dsp_init_riscv(OpusDSP *d)
@@ -37,6 +38,9 @@  av_cold void ff_opus_dsp_init_riscv(OpusDSP *d)
             case 16:
                 d->postfilter = ff_opus_postfilter_rvv_128;
+            case 32:
+                d->postfilter = ff_opus_postfilter_rvv_256;
+                break;
diff --git a/libavcodec/riscv/opusdsp_rvv.S b/libavcodec/riscv/opusdsp_rvv.S
index 79b46696cd..243c9a5e52 100644
--- a/libavcodec/riscv/opusdsp_rvv.S
+++ b/libavcodec/riscv/opusdsp_rvv.S
@@ -21,30 +21,38 @@ 
 #include "libavutil/riscv/asm.S"
 func ff_opus_postfilter_rvv_128, zve32f
+        lvtypei a5, e32, m2, ta, ma
+        j       1f
+func ff_opus_postfilter_rvv_256, zve32f
+        lvtypei a5, e32, m1, ta, ma
+        li           a4, 5
         addi         a1, a1, 2
         slli         a1, a1, 2
         lw           t1, 4(a2)
         vsetivli     zero, 3, e32, m1, ta, ma
         vle32.v      v24, (a2)
         sub          a1, a0, a1      // a1 = &x4 = &data[-(period + 2)]
-        vsetivli     zero, 5, e32, m2, ta, ma
+        vsetvl       zero, a4, a5
         vslide1up.vx v8, v24, t1
         lw           t2, 8(a2)
         vle32.v      v16, (a1)
         vslide1up.vx v24, v8, t2     // v24 = { g[2], g[1], g[0], g[1], g[2] }
-        vsetvli t0, a3, e32, m2, ta, ma
+        vsetvl  t0, a3, a5
         vle32.v v0, (a0)
         sub     a3, a3, t0
-        vsetivli       zero, 5, e32, m2, ta, ma
+        vsetvl         zero, a4, a5
         lw             t2, 20(a1)
         vfmul.vv       v8, v24, v16
         addi           a0, a0, 4
         vslide1down.vx v16, v16, t2
         addi           a1, a1, 4
         vfredusum.vs   v0, v8, v0
-        vsetvli        zero, t0, e32, m2, ta, ma
+        vsetvl         zero, t0, a5
         vmv.x.s        t1, v0
         addi           t0, t0, -1
         vslide1down.vx v0, v0, zero