From patchwork Wed Oct 5 16:12:55 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?R=C3=A9mi_Denis-Courmont?= X-Patchwork-Id: 38566 Delivered-To: ffmpegpatchwork2@gmail.com Received: by 2002:a05:6a20:4d9:b0:9c:f4b:4e41 with SMTP id 25csp700898pzd; Wed, 5 Oct 2022 09:13:24 -0700 (PDT) X-Google-Smtp-Source: AMsMyM5HPgmzAkGjkSR+WDynXCgw8pwUO0R+cfPIlzmoYjUz5AxN+P3G+S7yeVMBfeUZUqPajRbG X-Received: by 2002:a05:6402:2549:b0:452:8292:b610 with SMTP id l9-20020a056402254900b004528292b610mr460510edb.199.1664986404059; Wed, 05 Oct 2022 09:13:24 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1664986404; cv=none; d=google.com; s=arc-20160816; b=1Au6c1KUwkMAeklzJzk8w/YR+YuBYMkotvLdJ1/pTuHcTy/SPWya7StQOvFbOp1K4l a4kb6m1d6dXdcXR3esTD7TCu2kvez6aa8CLbJyzP22w8o+TsNfYobS1RChkX2nJXyJkw YrRKKYobM59VSGPWwpBKZOMZp867bRYCdSwF+S6p+j8RcDcnqjdpgFmEi3g1grQ9B69Q Yu2k2IuWupC0OI0yGIESoY7lSK+wK67q2b6VKRFGvMTRz16MsOaoXNZ9hNR3MRIt2Dpn 3JHEAW4n0333V7OHRGW3wlAZithJcPBUhLo1Pz2BY5ZOQu07oXNnxpnI1k1Xtnsoe2a8 QcNQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:reply-to:list-subscribe :list-help:list-post:list-archive:list-unsubscribe:list-id :precedence:subject:mime-version:references:in-reply-to:message-id :date:to:from:delivered-to; bh=HPqt4qZScekHfqdo91Dv0uMXKSEKH6dqxdP2SnuYzq0=; b=uIHNihSKM2F5s+ZqZSqtkPOfBvgvy/2qZ3n8agdFE1k5fxmpMHNk+jiXXG2zLtMh40 UNdF6cqapPFRY8qTdlV9PJpNeEw6IHewOe7DWoujf4vQx2/cQ7CG4TX+R94y6BbatZrI fQ/4WHu4wo/X0+kHVhSFxQdG4h9VztglA10JroyoZ7E676SU/r47eB83e+ugN+xkjy03 E7NFqKx/1+5X0U/KrHg00pc+JnasRxkcE0GVwqJ3F3DDE3Yr3Jeiyx6QKWQ+2kNVwl/M +cpqPqfmMiflAbV4cbeZNfl9EWl82l4JbGkcVu3bEAmO1D1nVc25rZBXKTodesWPAMZy 4NTQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of ffmpeg-devel-bounces@ffmpeg.org designates 79.124.17.100 as permitted sender) smtp.mailfrom=ffmpeg-devel-bounces@ffmpeg.org Return-Path: Received: from ffbox0-bg.mplayerhq.hu (ffbox0-bg.ffmpeg.org. [79.124.17.100]) by mx.google.com with ESMTP id z16-20020a05640235d000b004574154f09asi412341edc.529.2022.10.05.09.13.23; Wed, 05 Oct 2022 09:13:24 -0700 (PDT) Received-SPF: pass (google.com: domain of ffmpeg-devel-bounces@ffmpeg.org designates 79.124.17.100 as permitted sender) client-ip=79.124.17.100; Authentication-Results: mx.google.com; spf=pass (google.com: domain of ffmpeg-devel-bounces@ffmpeg.org designates 79.124.17.100 as permitted sender) smtp.mailfrom=ffmpeg-devel-bounces@ffmpeg.org Received: from [127.0.1.1] (localhost [127.0.0.1]) by ffbox0-bg.mplayerhq.hu (Postfix) with ESMTP id F1DAB68BD24; Wed, 5 Oct 2022 19:13:01 +0300 (EEST) X-Original-To: ffmpeg-devel@ffmpeg.org Delivered-To: ffmpeg-devel@ffmpeg.org Received: from ursule.remlab.net (vps-a2bccee9.vps.ovh.net [51.75.19.47]) by ffbox0-bg.mplayerhq.hu (Postfix) with ESMTP id DB99868BD13 for ; Wed, 5 Oct 2022 19:12:57 +0300 (EEST) Received: from basile.remlab.net (localhost [IPv6:::1]) by ursule.remlab.net (Postfix) with ESMTP id 911C8C00AF for ; Wed, 5 Oct 2022 19:12:57 +0300 (EEST) From: =?utf-8?q?R=C3=A9mi_Denis-Courmont?= To: ffmpeg-devel@ffmpeg.org Date: Wed, 5 Oct 2022 19:12:55 +0300 Message-Id: <20221005161256.27612-3-remi@remlab.net> X-Mailer: git-send-email 2.37.2 In-Reply-To: <12083658.O9o76ZdvQC@basile.remlab.net> References: <12083658.O9o76ZdvQC@basile.remlab.net> MIME-Version: 1.0 Subject: [FFmpeg-devel] [PATCH 3/4] lavc/opusdsp: RISC-V V (256-bit) postfilter X-BeenThere: ffmpeg-devel@ffmpeg.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: FFmpeg development discussions and patches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: FFmpeg development discussions and patches Errors-To: ffmpeg-devel-bounces@ffmpeg.org Sender: "ffmpeg-devel" X-TUID: RL83YfNtrnhy This adds a variant of the postfilter for use with 256-bit vectors. As a single vector is then large enough to perform the scalar product, the group multipler is reduced to just one at run-time. The different vector type is passed via register. Unfortunately, there is no VSETIVL instruction, so the constant vector size (5) also needs to be passed via a register. --- libavcodec/riscv/opusdsp_init.c | 4 ++++ libavcodec/riscv/opusdsp_rvv.S | 16 ++++++++++++---- 2 files changed, 16 insertions(+), 4 deletions(-) diff --git a/libavcodec/riscv/opusdsp_init.c b/libavcodec/riscv/opusdsp_init.c index f1d2c871e3..e6f9505f77 100644 --- a/libavcodec/riscv/opusdsp_init.c +++ b/libavcodec/riscv/opusdsp_init.c @@ -26,6 +26,7 @@ #include "libavcodec/opusdsp.h" void ff_opus_postfilter_rvv_128(float *data, int period, float *g, int len); +void ff_opus_postfilter_rvv_256(float *data, int period, float *g, int len); av_cold void ff_opus_dsp_init_riscv(OpusDSP *d) { @@ -37,6 +38,9 @@ av_cold void ff_opus_dsp_init_riscv(OpusDSP *d) case 16: d->postfilter = ff_opus_postfilter_rvv_128; break; + case 32: + d->postfilter = ff_opus_postfilter_rvv_256; + break; } #endif } diff --git a/libavcodec/riscv/opusdsp_rvv.S b/libavcodec/riscv/opusdsp_rvv.S index 79b46696cd..243c9a5e52 100644 --- a/libavcodec/riscv/opusdsp_rvv.S +++ b/libavcodec/riscv/opusdsp_rvv.S @@ -21,30 +21,38 @@ #include "libavutil/riscv/asm.S" func ff_opus_postfilter_rvv_128, zve32f + lvtypei a5, e32, m2, ta, ma + j 1f +endfunc + +func ff_opus_postfilter_rvv_256, zve32f + lvtypei a5, e32, m1, ta, ma +1: + li a4, 5 addi a1, a1, 2 slli a1, a1, 2 lw t1, 4(a2) vsetivli zero, 3, e32, m1, ta, ma vle32.v v24, (a2) sub a1, a0, a1 // a1 = &x4 = &data[-(period + 2)] - vsetivli zero, 5, e32, m2, ta, ma + vsetvl zero, a4, a5 vslide1up.vx v8, v24, t1 lw t2, 8(a2) vle32.v v16, (a1) vslide1up.vx v24, v8, t2 // v24 = { g[2], g[1], g[0], g[1], g[2] } 2: - vsetvli t0, a3, e32, m2, ta, ma + vsetvl t0, a3, a5 vle32.v v0, (a0) sub a3, a3, t0 3: - vsetivli zero, 5, e32, m2, ta, ma + vsetvl zero, a4, a5 lw t2, 20(a1) vfmul.vv v8, v24, v16 addi a0, a0, 4 vslide1down.vx v16, v16, t2 addi a1, a1, 4 vfredusum.vs v0, v8, v0 - vsetvli zero, t0, e32, m2, ta, ma + vsetvl zero, t0, a5 vmv.x.s t1, v0 addi t0, t0, -1 vslide1down.vx v0, v0, zero