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[79.124.17.100]) by mx.google.com with ESMTP id nb34-20020a1709071ca200b0073c100331cbsi19712463ejc.384.2022.10.06.00.38.14; Thu, 06 Oct 2022 00:38:14 -0700 (PDT) Received-SPF: pass (google.com: domain of ffmpeg-devel-bounces@ffmpeg.org designates 79.124.17.100 as permitted sender) client-ip=79.124.17.100; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@intel.com header.s=Intel header.b=jGN7Oxpg; spf=pass (google.com: domain of ffmpeg-devel-bounces@ffmpeg.org designates 79.124.17.100 as permitted sender) smtp.mailfrom=ffmpeg-devel-bounces@ffmpeg.org Received: from [127.0.1.1] (localhost [127.0.0.1]) by ffbox0-bg.mplayerhq.hu (Postfix) with ESMTP id 1B7DB68BBBA; Thu, 6 Oct 2022 10:38:10 +0300 (EEST) X-Original-To: ffmpeg-devel@ffmpeg.org Delivered-To: ffmpeg-devel@ffmpeg.org Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by ffbox0-bg.mplayerhq.hu (Postfix) with ESMTPS id BE7BA68B726 for ; Thu, 6 Oct 2022 10:38:02 +0300 (EEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1665041888; x=1696577888; h=from:to:cc:subject:date:message-id; bh=HegEkV9lSTUuN0VftaMxLDlCZmkVJSaICO30tiVG4t4=; b=jGN7Oxpg8jFF0FrLes/+tpH4+Yt8r/D1OD6B/0jO+vIljVm4vQ54HGuS bdXPF/Qt4a0mAi2qxUHfKmlykTiSB2jjyvQAlOyBsIZrsyvNg5X8CTFYu gF/+imuuA6nUfTynuD+0kmzH1lPGa6WvEEJ7J545tAz8/B7z3m5Wz7w+S a7mB1iwI1ZsQrFMgIzA+Dww3k4H1erhCHJWuSURuoqQPyj+3QWQ+y+hKF +UFtktuhtkAHlal8L7ci3GFGHTL8SE4eB+/7A+Vk18ETZ3NDZAT0nVmdf 63TpqiTQn5Qe5aL8gzL4NG3G/fQKdJP/dh7EB7j6iXYEPuyOhA89GTR/A A==; X-IronPort-AV: E=McAfee;i="6500,9779,10491"; a="300974384" X-IronPort-AV: E=Sophos;i="5.95,163,1661842800"; d="scan'208";a="300974384" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Oct 2022 00:38:00 -0700 X-IronPort-AV: E=McAfee;i="6500,9779,10491"; a="687318967" X-IronPort-AV: E=Sophos;i="5.95,163,1661842800"; d="scan'208";a="687318967" Received: from xhh-dg164.sh.intel.com ([10.238.5.169]) by fmsmga008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Oct 2022 00:37:59 -0700 From: "Xiang, Haihao" To: ffmpeg-devel@ffmpeg.org Date: Thu, 6 Oct 2022 15:35:33 +0800 Message-Id: <20221006073538.27710-1-haihao.xiang@intel.com> X-Mailer: git-send-email 2.17.1 Subject: [FFmpeg-devel] [PATCH 1/6] lavu/hwcontext_qsv: specify Shift for each format X-BeenThere: ffmpeg-devel@ffmpeg.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: FFmpeg development discussions and patches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: FFmpeg development discussions and patches Cc: Haihao Xiang MIME-Version: 1.0 Errors-To: ffmpeg-devel-bounces@ffmpeg.org Sender: "ffmpeg-devel" X-TUID: KmRxikKNQziN From: Haihao Xiang We can't get Shift from bit depth for some formats in the SDK. For example, bit depth is 10, however Shift is 0 for Y410 (XV30 in FFmpeg). In order to support these formats in the next commits, this patch specified Shift for each format Signed-off-by: Haihao Xiang --- libavutil/hwcontext_qsv.c | 27 +++++++++++++++++++-------- 1 file changed, 19 insertions(+), 8 deletions(-) diff --git a/libavutil/hwcontext_qsv.c b/libavutil/hwcontext_qsv.c index 9fa0dfa1c0..2272df52f2 100644 --- a/libavutil/hwcontext_qsv.c +++ b/libavutil/hwcontext_qsv.c @@ -109,20 +109,21 @@ typedef struct QSVFramesContext { static const struct { enum AVPixelFormat pix_fmt; uint32_t fourcc; + uint16_t mfx_shift; } supported_pixel_formats[] = { - { AV_PIX_FMT_NV12, MFX_FOURCC_NV12 }, - { AV_PIX_FMT_BGRA, MFX_FOURCC_RGB4 }, - { AV_PIX_FMT_P010, MFX_FOURCC_P010 }, - { AV_PIX_FMT_PAL8, MFX_FOURCC_P8 }, + { AV_PIX_FMT_NV12, MFX_FOURCC_NV12, 0 }, + { AV_PIX_FMT_BGRA, MFX_FOURCC_RGB4, 0 }, + { AV_PIX_FMT_P010, MFX_FOURCC_P010, 1 }, + { AV_PIX_FMT_PAL8, MFX_FOURCC_P8, 0 }, #if CONFIG_VAAPI { AV_PIX_FMT_YUYV422, - MFX_FOURCC_YUY2 }, + MFX_FOURCC_YUY2, 0 }, { AV_PIX_FMT_Y210, - MFX_FOURCC_Y210 }, + MFX_FOURCC_Y210, 1 }, // VUYX is used for VAAPI child device, // the SDK only delares support for AYUV { AV_PIX_FMT_VUYX, - MFX_FOURCC_AYUV }, + MFX_FOURCC_AYUV, 0 }, #endif }; @@ -170,6 +171,16 @@ static uint32_t qsv_fourcc_from_pix_fmt(enum AVPixelFormat pix_fmt) return 0; } +static uint16_t qsv_shift_from_pix_fmt(enum AVPixelFormat pix_fmt) +{ + for (int i = 0; i < FF_ARRAY_ELEMS(supported_pixel_formats); i++) { + if (supported_pixel_formats[i].pix_fmt == pix_fmt) + return supported_pixel_formats[i].mfx_shift; + } + + return 0; +} + #if CONFIG_D3D11VA static uint32_t qsv_get_d3d11va_bind_flags(int mem_type) { @@ -503,7 +514,7 @@ static int qsv_init_surface(AVHWFramesContext *ctx, mfxFrameSurface1 *surf) surf->Info.BitDepthLuma = desc->comp[0].depth; surf->Info.BitDepthChroma = desc->comp[0].depth; - surf->Info.Shift = desc->comp[0].depth > 8; + surf->Info.Shift = qsv_shift_from_pix_fmt(ctx->sw_format); if (desc->log2_chroma_w && desc->log2_chroma_h) surf->Info.ChromaFormat = MFX_CHROMAFORMAT_YUV420;