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[79.124.17.100]) by mx.google.com with ESMTP id b23-20020aa7cd17000000b004bb9fa855c6si3356236edw.503.2023.03.01.18.33.51; Wed, 01 Mar 2023 18:33:52 -0800 (PST) Received-SPF: pass (google.com: domain of ffmpeg-devel-bounces@ffmpeg.org designates 79.124.17.100 as permitted sender) client-ip=79.124.17.100; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@intel.com header.s=Intel header.b="OQp/zoMI"; spf=pass (google.com: domain of ffmpeg-devel-bounces@ffmpeg.org designates 79.124.17.100 as permitted sender) smtp.mailfrom=ffmpeg-devel-bounces@ffmpeg.org Received: from [127.0.1.1] (localhost [127.0.0.1]) by ffbox0-bg.mplayerhq.hu (Postfix) with ESMTP id 0E2DB68AB23; Thu, 2 Mar 2023 04:33:48 +0200 (EET) X-Original-To: ffmpeg-devel@ffmpeg.org Delivered-To: ffmpeg-devel@ffmpeg.org Received: from mga06.intel.com (mga06b.intel.com [134.134.136.31]) by ffbox0-bg.mplayerhq.hu (Postfix) with ESMTPS id D0CD368A31B for ; Thu, 2 Mar 2023 04:33:40 +0200 (EET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1677724427; x=1709260427; h=from:to:subject:date:message-id:mime-version: content-transfer-encoding; bh=8YvBVsbZK5B2X/1rfex3A/v1PpO5zEttGH1tnuCedcs=; b=OQp/zoMIke+ysAJ9Va2fyma6zjZ/AWD+Hwt6LoyNYWbix7yPy3Bj+Uil +h2DdC4iHVYB3TjHYFgXcZUUoLhjyKaM5/m57/opi1ZmP8CDC66cQLmUi 7WIUo7rAvYWC3LP6CZD06gA1axRTGAAxHtuZc03HrmplwXiqmQn2OWpsv 4UdCZY8rjszGRkyC/0pru0SQM5mzx8olFYMQSnjiMJlpsGWc/BRalv6Qi OZXDe9XbovP29XbViUlJ2UVCj6zgQ0pVzo3/sMcx5qoEqkAB0QOYpMjU8 jdzf8dxw8WA9rpMNIoN1Jf1/+IYn25adeF65B8bD7UjPaUMMDdPdz5EuJ g==; X-IronPort-AV: E=McAfee;i="6500,9779,10636"; a="397160300" X-IronPort-AV: E=Sophos;i="5.98,226,1673942400"; d="scan'208";a="397160300" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Mar 2023 18:33:38 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10636"; a="707248337" X-IronPort-AV: E=Sophos;i="5.98,226,1673942400"; d="scan'208";a="707248337" Received: from wenbin-z390-aorus-ultra.sh.intel.com ([10.239.35.4]) by orsmga001.jf.intel.com with ESMTP; 01 Mar 2023 18:33:37 -0800 From: wenbin.chen-at-intel.com@ffmpeg.org To: ffmpeg-devel@ffmpeg.org Date: Thu, 2 Mar 2023 10:33:36 +0800 Message-Id: <20230302023336.127035-1-wenbin.chen@intel.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Subject: [FFmpeg-devel] [PATCH] libavcodec/qsvenc: Add dynamic setting support of low_delay_brc to av1_qsv X-BeenThere: ffmpeg-devel@ffmpeg.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: FFmpeg development discussions and patches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: FFmpeg development discussions and patches Errors-To: ffmpeg-devel-bounces@ffmpeg.org Sender: "ffmpeg-devel" X-TUID: GP2GHKC/ZYtR From: Wenbin Chen Signed-off-by: Wenbin Chen --- doc/encoders.texi | 2 +- libavcodec/qsvenc.c | 5 ++++- 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/doc/encoders.texi b/doc/encoders.texi index b02737b9df..e9b34010ed 100644 --- a/doc/encoders.texi +++ b/doc/encoders.texi @@ -3344,7 +3344,7 @@ Supported in h264_qsv. Change these value to reset qsv codec's max/min qp configuration. @item @var{low_delay_brc} -Supported in h264_qsv and hevc_qsv. +Supported in h264_qsv, hevc_qsv and av1_qsv. Change this value to reset qsv codec's low_delay_brc configuration. @item @var{framerate} diff --git a/libavcodec/qsvenc.c b/libavcodec/qsvenc.c index 3607859cb8..c975302b4f 100644 --- a/libavcodec/qsvenc.c +++ b/libavcodec/qsvenc.c @@ -1127,6 +1127,7 @@ static int init_video_param(AVCodecContext *avctx, QSVEncContext *q) } else if (avctx->codec_id == AV_CODEC_ID_AV1) { if (q->low_delay_brc >= 0) q->extco3.LowDelayBRC = q->low_delay_brc ? MFX_CODINGOPTION_ON : MFX_CODINGOPTION_OFF; + q->old_low_delay_brc = q->low_delay_brc; } if (avctx->codec_id == AV_CODEC_ID_HEVC) { @@ -2213,7 +2214,9 @@ static int update_low_delay_brc(AVCodecContext *avctx, QSVEncContext *q) { int updated = 0; - if (avctx->codec_id != AV_CODEC_ID_H264 && avctx->codec_id != AV_CODEC_ID_HEVC) + if (avctx->codec_id != AV_CODEC_ID_H264 && + avctx->codec_id != AV_CODEC_ID_HEVC && + avctx->codec_id != AV_CODEC_ID_AV1) return 0; UPDATE_PARAM(q->old_low_delay_brc, q->low_delay_brc);