From patchwork Tue Jun 20 14:59:33 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?R=C3=A9mi_Denis-Courmont?= X-Patchwork-Id: 42256 Delivered-To: ffmpegpatchwork2@gmail.com Received: by 2002:a05:6a20:be15:b0:121:b37c:e101 with SMTP id ge21csp1452234pzb; Tue, 20 Jun 2023 07:59:45 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ64p7F+DrBhUYF4hHx0Y90K7/olDUq/LIxgiWmCLsmEXv1nzSYa/+8s/1ALij420T1Iet0i X-Received: by 2002:a05:6402:190a:b0:51a:493e:3212 with SMTP id e10-20020a056402190a00b0051a493e3212mr8999874edz.17.1687273184693; Tue, 20 Jun 2023 07:59:44 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1687273184; cv=none; d=google.com; s=arc-20160816; b=bLq/NqmMSA0hw6ykT5DjDsC7lpreLgli3RMPe+r89sKPy+F1LMB6ColA4Yk48tMF1b MzYberrRhI8/jRyXSdx0Sl+ZqJI/4Lzk/knqAHRe8qP9RO68LcN6evzKrTBFWBcav6x6 TFGRXeFDWKQ6i1KjpIANaVsTdo6nydCmYu4q92/3Bj+gs8yRXwM4g/RghfMvJdaze6am km/OmT4++Hhy35Qw8umZuIhVaZyy5PTG5fECsIsffhr6c94oYz8ntt0a3PTwTAO6C1RG 6pBGbYXbhOHa888mcQtR3Oz+///eVRQqdUonq4aQGFnhMpzI1YhgNcgs++KUQRAwFGHo MUvg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:reply-to:list-subscribe :list-help:list-post:list-archive:list-unsubscribe:list-id :precedence:subject:mime-version:message-id:date:to:from :delivered-to; bh=gJyORa3Rxrhdck4iwLZAfqy0r4FER0YAHH1MLudMcmo=; b=egWcTE7JF4AzXxXFyWEruT+ZvRJxNlbcOUC8uZCTht5B8fN9DL1GgeXBaxGwvlPVnr IlbOR//fm6xUJcctdrYw4YjoAQSUlPFus7loM1FpLiWoQNvoSSfBXZZFj5P0Q3uNlnzK UlrvFBBRv+IW+Kn7kIrPtt6PAZgkU7um1vNL3Omd0V9dpGUO9Lzsz6Ng5WP6SyFCol8B UbpS8aUxJ+Zi+uLyyRU9QeP/kDcXQ72r2EukjH0vio2nfeysr8vi+zVuyRXqlej3WoTu Xigl5L+b7L4JCjZHGbvkWwDRTJuQqu7EQpQHcQi9NFAdiLagpArFMpyRi/8u5Pn7EdZW 19bA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of ffmpeg-devel-bounces@ffmpeg.org designates 79.124.17.100 as permitted sender) smtp.mailfrom=ffmpeg-devel-bounces@ffmpeg.org Return-Path: Received: from ffbox0-bg.mplayerhq.hu (ffbox0-bg.ffmpeg.org. [79.124.17.100]) by mx.google.com with ESMTP id n4-20020a056402060400b005105923ffbbsi1197164edv.326.2023.06.20.07.59.43; Tue, 20 Jun 2023 07:59:44 -0700 (PDT) Received-SPF: pass (google.com: domain of ffmpeg-devel-bounces@ffmpeg.org designates 79.124.17.100 as permitted sender) client-ip=79.124.17.100; Authentication-Results: mx.google.com; spf=pass (google.com: domain of ffmpeg-devel-bounces@ffmpeg.org designates 79.124.17.100 as permitted sender) smtp.mailfrom=ffmpeg-devel-bounces@ffmpeg.org Received: from [127.0.1.1] (localhost [127.0.0.1]) by ffbox0-bg.mplayerhq.hu (Postfix) with ESMTP id 0830568BF69; Tue, 20 Jun 2023 17:59:41 +0300 (EEST) X-Original-To: ffmpeg-devel@ffmpeg.org Delivered-To: ffmpeg-devel@ffmpeg.org Received: from ursule.remlab.net (vps-a2bccee9.vps.ovh.net [51.75.19.47]) by ffbox0-bg.mplayerhq.hu (Postfix) with ESMTP id 605FB68B9AB for ; Tue, 20 Jun 2023 17:59:34 +0300 (EEST) Received: from basile.remlab.net (localhost [IPv6:::1]) by ursule.remlab.net (Postfix) with ESMTP id C49B8C01D5 for ; Tue, 20 Jun 2023 17:59:33 +0300 (EEST) From: =?utf-8?q?R=C3=A9mi_Denis-Courmont?= To: ffmpeg-devel@ffmpeg.org Date: Tue, 20 Jun 2023 17:59:33 +0300 Message-Id: <20230620145933.20966-1-remi@remlab.net> X-Mailer: git-send-email 2.40.1 MIME-Version: 1.0 Subject: [FFmpeg-devel] [PATCH] DRAFT: riscv: add Linux riscv_hwprobe() X-BeenThere: ffmpeg-devel@ffmpeg.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: FFmpeg development discussions and patches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: FFmpeg development discussions and patches Errors-To: ffmpeg-devel-bounces@ffmpeg.org Sender: "ffmpeg-devel" X-TUID: N3AgGh2DmpCG --- configure | 2 ++ libavutil/riscv/cpu.c | 54 ++++++++++++++++++++++++++++++++----------- 2 files changed, 43 insertions(+), 13 deletions(-) diff --git a/configure b/configure index ed9efad985..8cad88cdd2 100755 --- a/configure +++ b/configure @@ -5412,6 +5412,8 @@ elif enabled ppc; then elif enabled riscv; then + check_headers sys/hwprobe.h + if test_cpp_condition stddef.h "__riscv_zbb"; then enable fast_clz fi diff --git a/libavutil/riscv/cpu.c b/libavutil/riscv/cpu.c index a9263dbb78..36432f9777 100644 --- a/libavutil/riscv/cpu.c +++ b/libavutil/riscv/cpu.c @@ -20,6 +20,7 @@ #include "libavutil/cpu.h" #include "libavutil/cpu_internal.h" +#include "libavutil/macros.h" #include "libavutil/log.h" #include "config.h" @@ -27,26 +28,53 @@ #include #define HWCAP_RV(letter) (1ul << ((letter) - 'A')) #endif +#ifdef HAVE_SYS_HWPROBE_H +#include +#endif int ff_get_cpu_flags_riscv(void) { int ret = 0; +#if defined (HAVE_SYS_HWPROBE_H) + struct riscv_hwprobe pairs[] = { + { RISCV_HWPROBE_KEY_BASE_BEHAVIOR, 0 }, + { RISCV_HWPROBE_KEY_IMA_EXT_0, 0 }, + }; + + if (riscv_hwprobe(pairs, FF_ARRAY_ELEMS(pairs), 0, NULL, 0) == 0) { + if (pairs[0].value & RISCV_HWPROBE_BASE_BEHAVIOR_IMA) { + ret |= AV_CPU_FLAG_RVI; + if (pairs[1].value & RISCV_HWPROBE_IMA_FD) + ret |= AV_FLAG_RVF | AV_FLAG_RVD; +# ifdef RISCV_HWPROBE_IMA_V + if (pairs[1].value & RISCV_HWPROBE_IMA_V) + ret |= AV_CPU_FLAG_RVV_I32 | AV_CPU_FLAG_RVV_I64 + | AV_CPU_FLAG_RVV_F32 | AV_CPU_FLAG_RVV_F64; +# endif +# ifdef RISCV_HWPROBE_EXT_ZBB + if (pairs[1].value & RISCV_HWPROBE_EXT_ZBB) + ret |= AV_FLAG_RVB_BASIC; +# endif + } else +#endif #if HAVE_GETAUXVAL - const unsigned long hwcap = getauxval(AT_HWCAP); + { + const unsigned long hwcap = getauxval(AT_HWCAP); - if (hwcap & HWCAP_RV('I')) - ret |= AV_CPU_FLAG_RVI; - if (hwcap & HWCAP_RV('F')) - ret |= AV_CPU_FLAG_RVF; - if (hwcap & HWCAP_RV('D')) - ret |= AV_CPU_FLAG_RVD; - if (hwcap & HWCAP_RV('B')) - ret |= AV_CPU_FLAG_RVB_BASIC; + if (hwcap & HWCAP_RV('I')) + ret |= AV_CPU_FLAG_RVI; + if (hwcap & HWCAP_RV('F')) + ret |= AV_CPU_FLAG_RVF; + if (hwcap & HWCAP_RV('D')) + ret |= AV_CPU_FLAG_RVD; + if (hwcap & HWCAP_RV('B')) + ret |= AV_CPU_FLAG_RVB_BASIC; - /* The V extension implies all Zve* functional subsets */ - if (hwcap & HWCAP_RV('V')) - ret |= AV_CPU_FLAG_RVV_I32 | AV_CPU_FLAG_RVV_I64 - | AV_CPU_FLAG_RVV_F32 | AV_CPU_FLAG_RVV_F64; + /* The V extension implies all Zve* functional subsets */ + if (hwcap & HWCAP_RV('V')) + ret |= AV_CPU_FLAG_RVV_I32 | AV_CPU_FLAG_RVV_I64 + | AV_CPU_FLAG_RVV_F32 | AV_CPU_FLAG_RVV_F64; + } #endif #ifdef __riscv_i