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[79.124.17.100]) by mx.google.com with ESMTP id o26-20020aa7c51a000000b0053641d17dc9si206568edq.487.2023.10.04.12.51.49; Wed, 04 Oct 2023 12:51:56 -0700 (PDT) Received-SPF: pass (google.com: domain of ffmpeg-devel-bounces@ffmpeg.org designates 79.124.17.100 as permitted sender) client-ip=79.124.17.100; Authentication-Results: mx.google.com; spf=pass (google.com: domain of ffmpeg-devel-bounces@ffmpeg.org designates 79.124.17.100 as permitted sender) smtp.mailfrom=ffmpeg-devel-bounces@ffmpeg.org Received: from [127.0.1.1] (localhost [127.0.0.1]) by ffbox0-bg.mplayerhq.hu (Postfix) with ESMTP id 0F64C68CB3F; Wed, 4 Oct 2023 22:51:21 +0300 (EEST) X-Original-To: ffmpeg-devel@ffmpeg.org Delivered-To: ffmpeg-devel@ffmpeg.org Received: from ursule.remlab.net (vps-a2bccee9.vps.ovh.net [51.75.19.47]) by ffbox0-bg.mplayerhq.hu (Postfix) with ESMTP id 65E3368CA92 for ; Wed, 4 Oct 2023 22:51:11 +0300 (EEST) Received: from basile.remlab.net (localhost [IPv6:::1]) by ursule.remlab.net (Postfix) with ESMTP id 09B5EC0190 for ; Wed, 4 Oct 2023 22:51:10 +0300 (EEST) From: =?utf-8?q?R=C3=A9mi_Denis-Courmont?= To: ffmpeg-devel@ffmpeg.org Date: Wed, 4 Oct 2023 22:51:10 +0300 Message-ID: <20231004195110.38615-4-remi@remlab.net> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231004195110.38615-1-remi@remlab.net> References: <20231004195110.38615-1-remi@remlab.net> MIME-Version: 1.0 Subject: [FFmpeg-devel] [PATCH 4/4] lavu/fixed_dsp: R-V V vector_fmul_window X-BeenThere: ffmpeg-devel@ffmpeg.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: FFmpeg development discussions and patches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: FFmpeg development discussions and patches Errors-To: ffmpeg-devel-bounces@ffmpeg.org Sender: "ffmpeg-devel" X-TUID: ZkfRKXBRVBTB --- libavutil/riscv/fixed_dsp_init.c | 6 +++++ libavutil/riscv/fixed_dsp_rvv.S | 44 ++++++++++++++++++++++++++++++++ 2 files changed, 50 insertions(+) diff --git a/libavutil/riscv/fixed_dsp_init.c b/libavutil/riscv/fixed_dsp_init.c index 02883b31d4..6469b45374 100644 --- a/libavutil/riscv/fixed_dsp_init.c +++ b/libavutil/riscv/fixed_dsp_init.c @@ -25,6 +25,9 @@ #include "libavutil/cpu.h" #include "libavutil/fixed_dsp.h" +void ff_vector_fmul_window_fixed_rvv(int32_t *dst, const int32_t *src0, + const int32_t *src1, const int32_t *win, + int len); void ff_vector_fmul_fixed_rvv(int *dst, const int *src0, const int *src1, int len); void ff_vector_fmul_reverse_fixed_rvv(int *dst, const int *src0, @@ -40,6 +43,9 @@ av_cold void ff_fixed_dsp_init_riscv(AVFixedDSPContext *fdsp) int flags = av_get_cpu_flags(); if ((flags & AV_CPU_FLAG_RVV_I32) && (flags & AV_CPU_FLAG_RVB_ADDR)) { + if (flags & AV_CPU_FLAG_RVV_I64) + fdsp->vector_fmul_window = ff_vector_fmul_window_fixed_rvv; + fdsp->vector_fmul = ff_vector_fmul_fixed_rvv; fdsp->vector_fmul_reverse = ff_vector_fmul_reverse_fixed_rvv; fdsp->vector_fmul_add = ff_vector_fmul_add_fixed_rvv; diff --git a/libavutil/riscv/fixed_dsp_rvv.S b/libavutil/riscv/fixed_dsp_rvv.S index d5d538239f..5b666016a0 100644 --- a/libavutil/riscv/fixed_dsp_rvv.S +++ b/libavutil/riscv/fixed_dsp_rvv.S @@ -20,6 +20,50 @@ #include "asm.S" +func ff_vector_fmul_window_fixed_rvv, zve64x + csrwi vxrm, 0 + vsetvli t0, zero, e16, m1, ta, ma + sh2add a2, a4, a2 + vid.v v0 + sh3add t3, a4, a3 + vadd.vi v0, v0, 1 + sh3add t0, a4, a0 +1: + vsetvli t2, a4, e16, m1, ta, ma + slli t4, t2, 2 + vrsub.vx v2, v0, t2 + sub t3, t3, t4 + vsetvli zero, zero, e32, m2, ta, ma + sub a2, a2, t4 + vle32.v v8, (t3) + sub t0, t0, t4 + vle32.v v4, (a2) + sub a4, a4, t2 + vrgatherei16.vv v28, v8, v2 + vle32.v v16, (a1) + add a1, a1, t4 + vrgatherei16.vv v20, v4, v2 + vle32.v v24, (a3) + add a3, a3, t4 + vwmul.vv v12, v16, v28 + vwmul.vv v8, v16, v24 + // vwnmsac.vv does _not_ exist so multiply & subtract separately + vwmul.vv v4, v20, v24 + vwmacc.vv v8, v20, v28 + vsetvli zero, zero, e64, m4, ta, ma + vsub.vv v12, v12, v4 + vsetvli zero, zero, e32, m2, ta, ma + vnclip.wi v16, v8, 31 + vnclip.wi v20, v12, 31 + vrgatherei16.vv v8, v16, v2 + vse32.v v20, (a0) + add a0, a0, t4 + vse32.v v8, (t0) + bnez a4, 1b + + ret +endfunc + func ff_vector_fmul_fixed_rvv, zve32x csrwi vxrm, 0 1: