From patchwork Wed Nov 15 18:02:20 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?R=C3=A9mi_Denis-Courmont?= X-Patchwork-Id: 44677 Delivered-To: ffmpegpatchwork2@gmail.com Received: by 2002:a05:6a20:92a5:b0:181:818d:5e7f with SMTP id q37csp2862816pzg; Wed, 15 Nov 2023 10:02:41 -0800 (PST) X-Google-Smtp-Source: AGHT+IHaQKHXbcauLbsi8g1RH1FfMuZ+eVUqm2D9KpHk4lApjsCn4CVLl4FQGBHLhiMwzTKdzbAl X-Received: by 2002:a17:906:18e1:b0:9e0:2319:16f0 with SMTP id e1-20020a17090618e100b009e0231916f0mr90590ejf.65.1700071361411; Wed, 15 Nov 2023 10:02:41 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1700071361; cv=none; d=google.com; s=arc-20160816; b=jLxi40kP9Beft89stuBvKkfSgeQFF0Ya7ugTopXNdBzISBEGBxzEX3jCXgZU1AX6Kd nTQv5FHRS0kmSpDBDPa8STH3sGtBzK8FO0TIlPVer3cdTcbSlBTNMHet2vaRaxt8jYx2 k5ByFqjLsREG+UxvGgVBCaKjREO+C5OdVgIBP3RJknxSJfksvdRk6FheCd2yAkzgQY0f QlHpThiS/WyEhfnpgNKdN27MAxS9gOEREx17ciiVjWzk1VbsLTNTSzjk1StiNxbCTDiq /T1gZNBXntE3ivf5/EiWvkJMpkj9td1hJPr0P6nfItKb48uKJh5rnDOjmH1f7eULF6+W StSg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:reply-to:list-subscribe :list-help:list-post:list-archive:list-unsubscribe:list-id :precedence:subject:mime-version:references:in-reply-to:message-id :date:to:from:delivered-to; bh=Xgp5aGUyxD1hyy8fzLkATA9aSYaExlwssAfGZfpG6/A=; fh=YOA8vD9MJZuwZ71F/05pj6KdCjf6jQRmzLS+CATXUQk=; b=ybEVdKsZDzZDMXOCmtNwTEUE+exLgenwP8Alfg2H4O53uOZ3CoDiISeruBUmH4ripV MM+6qINr80rv14bEwX0QfZQARWqX6AP0Xfn48/KJXror46pgZAPAkSMNXNeTaRkWBHNg MPZRaJUlUv6/EqOCJ4qzYEk5skgP3j6WP7qe9Z/8w0nX7Idm7jT7onPB2Jr3be/bAAPG Wqo+1Z2t3TjKNzQWdcEF5AOcqxmyuCgyB1jEWCUnJBN2F0Zzz2ntawCglmhTeGwUKqof 4x/Qdas2Zxg/orDxc+1Eu+sdGP+jzzBWghobqDR6jfUyGH03g/fRPUrnaNaB0Rrm99cR /gCQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of ffmpeg-devel-bounces@ffmpeg.org designates 79.124.17.100 as permitted sender) smtp.mailfrom=ffmpeg-devel-bounces@ffmpeg.org Return-Path: Received: from ffbox0-bg.mplayerhq.hu (ffbox0-bg.ffmpeg.org. [79.124.17.100]) by mx.google.com with ESMTP id f23-20020a17090624d700b009929566f00asi5571937ejb.467.2023.11.15.10.02.40; Wed, 15 Nov 2023 10:02:41 -0800 (PST) Received-SPF: pass (google.com: domain of ffmpeg-devel-bounces@ffmpeg.org designates 79.124.17.100 as permitted sender) client-ip=79.124.17.100; Authentication-Results: mx.google.com; spf=pass (google.com: domain of ffmpeg-devel-bounces@ffmpeg.org designates 79.124.17.100 as permitted sender) smtp.mailfrom=ffmpeg-devel-bounces@ffmpeg.org Received: from [127.0.1.1] (localhost [127.0.0.1]) by ffbox0-bg.mplayerhq.hu (Postfix) with ESMTP id 68C1968CC75; Wed, 15 Nov 2023 20:02:28 +0200 (EET) X-Original-To: ffmpeg-devel@ffmpeg.org Delivered-To: ffmpeg-devel@ffmpeg.org Received: from ursule.remlab.net (vps-a2bccee9.vps.ovh.net [51.75.19.47]) by ffbox0-bg.mplayerhq.hu (Postfix) with ESMTP id E72CA68CA60 for ; Wed, 15 Nov 2023 20:02:20 +0200 (EET) Received: from basile.remlab.net (localhost [IPv6:::1]) by ursule.remlab.net (Postfix) with ESMTP id 86210C0099 for ; Wed, 15 Nov 2023 20:02:20 +0200 (EET) From: =?utf-8?q?R=C3=A9mi_Denis-Courmont?= To: ffmpeg-devel@ffmpeg.org Date: Wed, 15 Nov 2023 20:02:20 +0200 Message-ID: <20231115180220.47256-2-remi@remlab.net> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231115180220.47256-1-remi@remlab.net> References: <20231115180220.47256-1-remi@remlab.net> MIME-Version: 1.0 Subject: [FFmpeg-devel] [PATCH 2/2] lavc/flacdsp: R-V V LPC32 X-BeenThere: ffmpeg-devel@ffmpeg.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: FFmpeg development discussions and patches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: FFmpeg development discussions and patches Errors-To: ffmpeg-devel-bounces@ffmpeg.org Sender: "ffmpeg-devel" X-TUID: 9pWtHlctzKYL The entire set of 32 coefficients and corresponding past 32 samples can fit in a single vector (with LMUL=8) exactly, but... since widening double the needed vector sizes, we still end up too short with 128-bit vectors. This adds a very simple version for future 256+-bit hardware, and for pred_orders values up to 16, and a bit more involved loop for for 128-bit hardware with pred_orders between 17 and 32. With 128-bit hardware, the benchmarks look like this: flac_lpc_32_13_c: 30152.0 flac_lpc_32_13_rvv_i32: 10244.7 flac_lpc_32_16_c: 37314.2 flac_lpc_32_16_rvv_i32: 10126.2 flac_lpc_32_29_c: 61910.0 flac_lpc_32_29_rvv_i32: 14495.2 flac_lpc_32_32_c: 68204.0 flac_lpc_32_32_rvv_i32: 13273.7 --- libavcodec/riscv/flacdsp_init.c | 12 +++++++ libavcodec/riscv/flacdsp_rvv.S | 57 +++++++++++++++++++++++++++++++++ 2 files changed, 69 insertions(+) diff --git a/libavcodec/riscv/flacdsp_init.c b/libavcodec/riscv/flacdsp_init.c index 73d431cb77..f60f98ea31 100644 --- a/libavcodec/riscv/flacdsp_init.c +++ b/libavcodec/riscv/flacdsp_init.c @@ -22,8 +22,13 @@ #include "libavutil/attributes.h" #include "libavutil/cpu.h" +#include "libavutil/riscv/cpu.h" #include "libavcodec/flacdsp.h" +void ff_flac_lpc32_rvv(int32_t *decoded, const int coeffs[32], + int pred_order, int qlevel, int len); +void ff_flac_lpc32_rvv_simple(int32_t *decoded, const int coeffs[32], + int pred_order, int qlevel, int len); void ff_flac_decorrelate_indep2_16_rvv(uint8_t **out, int32_t **in, int channels, int len, int shift); void ff_flac_decorrelate_indep4_16_rvv(uint8_t **out, int32_t **in, @@ -60,6 +65,13 @@ av_cold void ff_flacdsp_init_riscv(FLACDSPContext *c, enum AVSampleFormat fmt, int flags = av_get_cpu_flags(); if ((flags & AV_CPU_FLAG_RVV_I32) && (flags & AV_CPU_FLAG_RVB_ADDR)) { + int vlenb = ff_get_rv_vlenb(); + + if (vlenb == 16) + c->lpc32 = ff_flac_lpc32_rvv; + else if (vlenb > 16) + c->lpc32 = ff_flac_lpc32_rvv_simple; + switch (fmt) { case AV_SAMPLE_FMT_S16: switch (channels) { diff --git a/libavcodec/riscv/flacdsp_rvv.S b/libavcodec/riscv/flacdsp_rvv.S index 12b456f7da..b1724f5500 100644 --- a/libavcodec/riscv/flacdsp_rvv.S +++ b/libavcodec/riscv/flacdsp_rvv.S @@ -21,6 +21,63 @@ #include "libavutil/riscv/asm.S" #if (__riscv_xlen == 64) +func ff_flac_lpc32_rvv, zve32x + addi t2, a2, -16 + ble t2, zero, ff_flac_lpc32_rvv_simple + vsetivli zero, 1, e64, m1, ta, ma + vmv.s.x v0, zero + vsetvli zero, a2, e32, m8, ta, ma + vle32.v v8, (a1) + sub a4, a4, a2 + vle32.v v16, (a0) + sh2add a0, a2, a0 +1: + vsetvli zero, a2, e32, m4, ta, ma + vwmul.vv v24, v8, v16 + vsetvli zero, t2, e32, m4, tu, ma + vwmacc.vv v24, v12, v20 + vsetvli zero, a2, e64, m8, ta, ma + vredsum.vs v24, v24, v0 + lw t0, (a0) + addi a4, a4, -1 + vmv.x.s t1, v24 + vsetvli zero, a2, e32, m8, ta, ma + sra t1, t1, a3 + add t0, t0, t1 + vslide1down.vx v16, v16, t0 + sw t0, (a0) + addi a0, a0, 4 + bnez a4, 1b + + ret +endfunc + +func ff_flac_lpc32_rvv_simple, zve32x + vsetivli zero, 1, e64, m1, ta, ma + vmv.s.x v0, zero + vsetvli zero, a2, e32, m4, ta, ma + vle32.v v8, (a1) + sub a4, a4, a2 + vle32.v v16, (a0) + sh2add a0, a2, a0 +1: + vwmul.vv v24, v8, v16 + vsetvli zero, zero, e64, m8, ta, ma + vredsum.vs v24, v24, v0 + lw t0, (a0) + addi a4, a4, -1 + vmv.x.s t1, v24 + vsetvli zero, zero, e32, m4, ta, ma + sra t1, t1, a3 + add t0, t0, t1 + vslide1down.vx v16, v16, t0 + sw t0, (a0) + addi a0, a0, 4 + bnez a4, 1b + + ret +endfunc + func ff_flac_decorrelate_indep2_16_rvv, zve32x ld a0, (a0) ld a2, 8(a1)