diff mbox series

[FFmpeg-devel,v2] riscv: vc1dsp: Don't check vlenb before checking the CPU flags

Message ID 20231215153845.161544-1-martin@martin.st
State Accepted
Commit b51d9eb58eae046b08ef0a967ab2d3e863047d74
Headers show
Series [FFmpeg-devel,v2] riscv: vc1dsp: Don't check vlenb before checking the CPU flags | expand

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Commit Message

Martin Storsjö Dec. 15, 2023, 3:38 p.m. UTC 
We can't call ff_get_rv_vlenb() if we don't have RVV available
at all.

Due to the SIGILL signal handler in checkasm catching it, in an
unexpected place, this caused checkasm to hang instead of reporting
the issue.
---
 libavcodec/riscv/vc1dsp_init.c | 8 +++-----
 1 file changed, 3 insertions(+), 5 deletions(-)

Comments

Rémi Denis-Courmont Dec. 16, 2023, 8:51 a.m. UTC | #1 
Le perjantaina 15. joulukuuta 2023, 17.38.45 EET Martin Storsjö a écrit :
> We can't call ff_get_rv_vlenb() if we don't have RVV available
> at all.
> 
> Due to the SIGILL signal handler in checkasm catching it, in an
> unexpected place, this caused checkasm to hang instead of reporting
> the issue.
> ---
>  libavcodec/riscv/vc1dsp_init.c | 8 +++-----
>  1 file changed, 3 insertions(+), 5 deletions(-)
> 
> diff --git a/libavcodec/riscv/vc1dsp_init.c b/libavcodec/riscv/vc1dsp_init.c
> index 0d22d28f4d..e47b644f80 100644
> --- a/libavcodec/riscv/vc1dsp_init.c
> +++ b/libavcodec/riscv/vc1dsp_init.c
> @@ -35,15 +35,13 @@ av_cold void ff_vc1dsp_init_riscv(VC1DSPContext *dsp)
>  #if HAVE_RVV
>      int flags = av_get_cpu_flags();
> 
> -    if (ff_get_rv_vlenb() >= 16) {
> +    if (flags & AV_CPU_FLAG_RVV_I32 && ff_get_rv_vlenb() >= 16) {
> +        dsp->vc1_inv_trans_4x8_dc = ff_vc1_inv_trans_4x8_dc_rvv;
> +        dsp->vc1_inv_trans_4x4_dc = ff_vc1_inv_trans_4x4_dc_rvv;
>          if (flags & AV_CPU_FLAG_RVV_I64) {
>              dsp->vc1_inv_trans_8x8_dc = ff_vc1_inv_trans_8x8_dc_rvv;
>              dsp->vc1_inv_trans_8x4_dc = ff_vc1_inv_trans_8x4_dc_rvv;
>          }
> -        if (flags & AV_CPU_FLAG_RVV_I32) {
> -            dsp->vc1_inv_trans_4x8_dc = ff_vc1_inv_trans_4x8_dc_rvv;
> -            dsp->vc1_inv_trans_4x4_dc = ff_vc1_inv_trans_4x4_dc_rvv;
> -        }
>      }
>  #endif
>  }

Acked-by: Rémi Denis-Courmont <remi@remlab.net>
Martin Storsjö Dec. 16, 2023, 8:31 p.m. UTC | #2 
On Sat, 16 Dec 2023, Rémi Denis-Courmont wrote:

> Le perjantaina 15. joulukuuta 2023, 17.38.45 EET Martin Storsjö a écrit :
>> We can't call ff_get_rv_vlenb() if we don't have RVV available
>> at all.
>> 
>> Due to the SIGILL signal handler in checkasm catching it, in an
>> unexpected place, this caused checkasm to hang instead of reporting
>> the issue.
>> ---
>>  libavcodec/riscv/vc1dsp_init.c | 8 +++-----
>>  1 file changed, 3 insertions(+), 5 deletions(-)
>> 
>> diff --git a/libavcodec/riscv/vc1dsp_init.c b/libavcodec/riscv/vc1dsp_init.c
>> index 0d22d28f4d..e47b644f80 100644
>> --- a/libavcodec/riscv/vc1dsp_init.c
>> +++ b/libavcodec/riscv/vc1dsp_init.c
>> @@ -35,15 +35,13 @@ av_cold void ff_vc1dsp_init_riscv(VC1DSPContext *dsp)
>>  #if HAVE_RVV
>>      int flags = av_get_cpu_flags();
>> 
>> -    if (ff_get_rv_vlenb() >= 16) {
>> +    if (flags & AV_CPU_FLAG_RVV_I32 && ff_get_rv_vlenb() >= 16) {
>> +        dsp->vc1_inv_trans_4x8_dc = ff_vc1_inv_trans_4x8_dc_rvv;
>> +        dsp->vc1_inv_trans_4x4_dc = ff_vc1_inv_trans_4x4_dc_rvv;
>>          if (flags & AV_CPU_FLAG_RVV_I64) {
>>              dsp->vc1_inv_trans_8x8_dc = ff_vc1_inv_trans_8x8_dc_rvv;
>>              dsp->vc1_inv_trans_8x4_dc = ff_vc1_inv_trans_8x4_dc_rvv;
>>          }
>> -        if (flags & AV_CPU_FLAG_RVV_I32) {
>> -            dsp->vc1_inv_trans_4x8_dc = ff_vc1_inv_trans_4x8_dc_rvv;
>> -            dsp->vc1_inv_trans_4x4_dc = ff_vc1_inv_trans_4x4_dc_rvv;
>> -        }
>>      }
>>  #endif
>>  }
>
> Acked-by: Rémi Denis-Courmont <remi@remlab.net>

Thanks, pushed.

// Martin
diff mbox series

Patch

diff --git a/libavcodec/riscv/vc1dsp_init.c b/libavcodec/riscv/vc1dsp_init.c
index 0d22d28f4d..e47b644f80 100644
--- a/libavcodec/riscv/vc1dsp_init.c
+++ b/libavcodec/riscv/vc1dsp_init.c
@@ -35,15 +35,13 @@  av_cold void ff_vc1dsp_init_riscv(VC1DSPContext *dsp)
 #if HAVE_RVV
     int flags = av_get_cpu_flags();
 
-    if (ff_get_rv_vlenb() >= 16) {
+    if (flags & AV_CPU_FLAG_RVV_I32 && ff_get_rv_vlenb() >= 16) {
+        dsp->vc1_inv_trans_4x8_dc = ff_vc1_inv_trans_4x8_dc_rvv;
+        dsp->vc1_inv_trans_4x4_dc = ff_vc1_inv_trans_4x4_dc_rvv;
         if (flags & AV_CPU_FLAG_RVV_I64) {
             dsp->vc1_inv_trans_8x8_dc = ff_vc1_inv_trans_8x8_dc_rvv;
             dsp->vc1_inv_trans_8x4_dc = ff_vc1_inv_trans_8x4_dc_rvv;
         }
-        if (flags & AV_CPU_FLAG_RVV_I32) {
-            dsp->vc1_inv_trans_4x8_dc = ff_vc1_inv_trans_4x8_dc_rvv;
-            dsp->vc1_inv_trans_4x4_dc = ff_vc1_inv_trans_4x4_dc_rvv;
-        }
     }
 #endif
 }