diff mbox series

[FFmpeg-devel,1/2] lavu/riscv: CPU flag for fast misaligned accesses

Message ID 20240511155142.59542-1-remi@remlab.net
State Accepted
Commit b410439263e1018912581c8ff672e3f0ed800875
Headers show
Series [FFmpeg-devel,1/2] lavu/riscv: CPU flag for fast misaligned accesses | expand

Commit Message

Rémi Denis-Courmont May 11, 2024, 3:51 p.m. UTC 
---
 libavutil/cpu.c           | 1 +
 libavutil/cpu.h           | 1 +
 libavutil/riscv/cpu.c     | 3 +++
 libavutil/tests/cpu.c     | 3 ++-
 tests/checkasm/checkasm.c | 1 +
 5 files changed, 8 insertions(+), 1 deletion(-)
diff mbox series

Patch

diff --git a/libavutil/cpu.c b/libavutil/cpu.c
index 396eeb38d6..9ac2f01c20 100644
--- a/libavutil/cpu.c
+++ b/libavutil/cpu.c
@@ -193,6 +193,7 @@  int av_parse_cpu_caps(unsigned *flags, const char *s)
         { "zba",      NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_RVB_ADDR },    .unit = "flags" },
         { "zbb",      NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_RVB_BASIC },   .unit = "flags" },
         { "zvbb",     NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_RV_ZVBB },   .unit = "flags" },
+        { "misaligned", NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_RV_MISALIGNED },   .unit = "flags" },
 #endif
         { NULL },
     };
diff --git a/libavutil/cpu.h b/libavutil/cpu.h
index cc19828d4b..a25901433e 100644
--- a/libavutil/cpu.h
+++ b/libavutil/cpu.h
@@ -91,6 +91,7 @@ 
 #define AV_CPU_FLAG_RVB_BASIC    (1 << 7) ///< Basic bit-manipulations
 #define AV_CPU_FLAG_RVB_ADDR     (1 << 8) ///< Address bit-manipulations
 #define AV_CPU_FLAG_RV_ZVBB      (1 << 9) ///< Vector basic bit-manipulations
+#define AV_CPU_FLAG_RV_MISALIGNED (1 <<10) ///< Fast misaligned accesses
 
 /**
  * Return the flags which specify extensions supported by the CPU.
diff --git a/libavutil/riscv/cpu.c b/libavutil/riscv/cpu.c
index 6755f0df69..1fe1a397c4 100644
--- a/libavutil/riscv/cpu.c
+++ b/libavutil/riscv/cpu.c
@@ -52,6 +52,7 @@  int ff_get_cpu_flags_riscv(void)
     struct riscv_hwprobe pairs[] = {
         { RISCV_HWPROBE_KEY_BASE_BEHAVIOR, 0 },
         { RISCV_HWPROBE_KEY_IMA_EXT_0, 0 },
+        { RISCV_HWPROBE_KEY_CPUPERF_0, 0 },
     };
 
     if (__riscv_hwprobe(pairs, FF_ARRAY_ELEMS(pairs), 0, NULL, 0) == 0) {
@@ -76,6 +77,8 @@  int ff_get_cpu_flags_riscv(void)
         if (pairs[1].value & RISCV_HWPROBE_EXT_ZVBB)
             ret |= AV_CPU_FLAG_RV_ZVBB;
 #endif
+        if (pairs[2].value & RISCV_HWPROBE_MISALIGNED_FAST)
+            ret |= AV_CPU_FLAG_RV_MISALIGNED;
     } else
 #endif
 #if HAVE_GETAUXVAL
diff --git a/libavutil/tests/cpu.c b/libavutil/tests/cpu.c
index 10e620963b..02b98682e3 100644
--- a/libavutil/tests/cpu.c
+++ b/libavutil/tests/cpu.c
@@ -94,7 +94,8 @@  static const struct {
     { AV_CPU_FLAG_RVV_F32,   "zve32f"     },
     { AV_CPU_FLAG_RVV_I64,   "zve64x"     },
     { AV_CPU_FLAG_RVV_F64,   "zve64d"     },
-    { AV_CPU_FLAG_RV_ZVBB,   "zvbb"      },
+    { AV_CPU_FLAG_RV_ZVBB,   "zvbb"       },
+    { AV_CPU_FLAG_RV_MISALIGNED, "misaligned" },
 #endif
     { 0 }
 };
diff --git a/tests/checkasm/checkasm.c b/tests/checkasm/checkasm.c
index 04f94f9d09..c6dc0cfa77 100644
--- a/tests/checkasm/checkasm.c
+++ b/tests/checkasm/checkasm.c
@@ -286,6 +286,7 @@  static const struct {
     { "RVVi64",   "rvv_i64",  AV_CPU_FLAG_RVV_I64 },
     { "RVVf64",   "rvv_f64",  AV_CPU_FLAG_RVV_F64 },
     { "RV_Zvbb",  "rv_zvbb",  AV_CPU_FLAG_RV_ZVBB },
+    { "misaligned", "misaligned", AV_CPU_FLAG_RV_MISALIGNED },
 #elif ARCH_MIPS
     { "MMI",      "mmi",      AV_CPU_FLAG_MMI },
     { "MSA",      "msa",      AV_CPU_FLAG_MSA },