diff mbox series

[FFmpeg-devel,2/2] lavc/vp8dsp: restrict RVI optimisations

Message ID 20240511155142.59542-2-remi@remlab.net
State Accepted
Commit 9d3f561721cd710bf403af991a0e36ccc9e8d8c8
Headers show
Series [FFmpeg-devel,1/2] lavu/riscv: CPU flag for fast misaligned accesses | expand

Commit Message

Rémi Denis-Courmont May 11, 2024, 3:51 p.m. UTC 
They are actually awfully slow if the CPU does not support misaligned
accesses natively, so only use them if misaligned accesses are fast.
---
 libavcodec/riscv/vp8dsp_init.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
diff mbox series

Patch

diff --git a/libavcodec/riscv/vp8dsp_init.c b/libavcodec/riscv/vp8dsp_init.c
index dc3e087f01..fe4fa5b867 100644
--- a/libavcodec/riscv/vp8dsp_init.c
+++ b/libavcodec/riscv/vp8dsp_init.c
@@ -45,7 +45,7 @@  av_cold void ff_vp78dsp_init_riscv(VP8DSPContext *c)
 {
 #if HAVE_RV
     int flags = av_get_cpu_flags();
-    if (flags & AV_CPU_FLAG_RVI) {
+    if (flags & AV_CPU_FLAG_RV_MISALIGNED) {
 #if __riscv_xlen >= 64
         c->put_vp8_epel_pixels_tab[0][0][0] = ff_put_vp8_pixels16_rvi;
         c->put_vp8_epel_pixels_tab[1][0][0] = ff_put_vp8_pixels8_rvi;