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[79.124.17.100]) by mx.google.com with ESMTP id 2adb3069b0e04-52e7ab28fedsi1679619e87.346.2024.06.30.05.12.50; Sun, 30 Jun 2024 05:12:50 -0700 (PDT) Received-SPF: pass (google.com: domain of ffmpeg-devel-bounces@ffmpeg.org designates 79.124.17.100 as permitted sender) client-ip=79.124.17.100; Authentication-Results: mx.google.com; spf=pass (google.com: domain of ffmpeg-devel-bounces@ffmpeg.org designates 79.124.17.100 as permitted sender) smtp.mailfrom=ffmpeg-devel-bounces@ffmpeg.org Received: from [127.0.1.1] (localhost [127.0.0.1]) by ffbox0-bg.mplayerhq.hu (Postfix) with ESMTP id 46A4E68D69D; Sun, 30 Jun 2024 14:55:07 +0300 (EEST) X-Original-To: ffmpeg-devel@ffmpeg.org Delivered-To: ffmpeg-devel@ffmpeg.org Received: from ursule.remlab.net (vps-a2bccee9.vps.ovh.net [51.75.19.47]) by ffbox0-bg.mplayerhq.hu (Postfix) with ESMTP id 101A868D109 for ; Sun, 30 Jun 2024 14:54:57 +0300 (EEST) Received: from basile.remlab.net (localhost [IPv6:::1]) by ursule.remlab.net (Postfix) with ESMTP id 73C4EC0145 for ; Sun, 30 Jun 2024 14:54:56 +0300 (EEST) From: =?utf-8?q?R=C3=A9mi_Denis-Courmont?= To: ffmpeg-devel@ffmpeg.org Date: Sun, 30 Jun 2024 14:54:56 +0300 Message-ID: <20240630115456.100163-2-remi@remlab.net> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240630115456.100163-1-remi@remlab.net> References: <20240630115456.100163-1-remi@remlab.net> MIME-Version: 1.0 Subject: [FFmpeg-devel] [PATCH 2/2] lavc/vc1dsp: fuse multiply-adds in R-V V inv_trans_8 X-BeenThere: ffmpeg-devel@ffmpeg.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: FFmpeg development discussions and patches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: FFmpeg development discussions and patches Errors-To: ffmpeg-devel-bounces@ffmpeg.org Sender: "ffmpeg-devel" X-TUID: kkHl8SjRV80V --- libavcodec/riscv/vc1dsp_rvv.S | 63 +++++++++++++++-------------------- 1 file changed, 27 insertions(+), 36 deletions(-) diff --git a/libavcodec/riscv/vc1dsp_rvv.S b/libavcodec/riscv/vc1dsp_rvv.S index 8c127c7644..d8b62579aa 100644 --- a/libavcodec/riscv/vc1dsp_rvv.S +++ b/libavcodec/riscv/vc1dsp_rvv.S @@ -116,55 +116,46 @@ endfunc .variant_cc ff_vc1_inv_trans_8_rvv func ff_vc1_inv_trans_8_rvv, zve32x li t4, 12 - vsll.vi v18, v6, 4 + vsll.vi v14, v6, 4 li t2, 6 - vmul.vx v8, v0, t4 + vsll.vi v12, v2, 4 li t5, 15 - vmul.vx v10, v4, t4 + vmul.vx v8, v0, t4 li t3, 9 # t[2..5] = [6 9 12 15] - vsll.vi v12, v2, 4 - vmul.vx v14, v6, t2 + vmul.vx v10, v4, t4 vmul.vx v16, v2, t2 - vadd.vv v26, v12, v14 # t3 + vmacc.vx v12, t2, v6 # t3 + vnmsac.vx v14, t2, v2 # -t4 vadd.vv v24, v8, v10 # t1 vsub.vv v25, v8, v10 # t2 - vsub.vv v27, v16, v18 # t4 - vadd.vv v28, v24, v26 # t5 - vsub.vv v31, v24, v26 # t8 - vadd.vv v29, v25, v27 # t6 - vsub.vv v30, v25, v27 # t7 + vadd.vv v28, v24, v12 # t5 + vsub.vv v31, v24, v12 # t8 + vsub.vv v29, v25, v14 # t6 + vadd.vv v30, v25, v14 # t7 vsll.vi v20, v1, 4 - vmul.vx v21, v3, t5 - vmul.vx v22, v5, t3 - vsll.vi v23, v7, 2 - vadd.vv v20, v20, v21 - vadd.vv v22, v22, v23 + vsll.vi v22, v7, 2 + vmacc.vx v20, t5, v3 + vmacc.vx v22, t3, v5 vsll.vi v21, v3, 2 + vsll.vi v23, v5, 4 vadd.vv v24, v20, v22 # t1 - vmul.vx v20, v1, t5 - vsll.vi v22, v5, 4 - vmul.vx v23, v7, t3 - vsub.vv v20, v20, v21 - vadd.vv v22, v22, v23 - vsll.vi v21, v3, 4 - vsub.vv v25, v20, v22 # t2 - vmul.vx v20, v1, t3 + vnmsac.vx v21, t5, v1 + vmacc.vx v23, t3, v7 + vsll.vi v20, v3, 4 vsll.vi v22, v5, 2 - vmul.vx v23, v7, t5 - vsub.vv v20, v20, v21 - vadd.vv v22, v22, v23 - vmul.vx v21, v3, t3 - vadd.vv v26, v20, v22 # t3 - vsll.vi v20, v1, 2 - vmul.vx v22, v5, t5 + vadd.vv v25, v21, v23 # -t2 + vnmsac.vx v20, t3, v1 + vmacc.vx v22, t5, v7 + vsll.vi v21, v1, 2 vsll.vi v23, v7, 4 - vsub.vv v20, v20, v21 - vsub.vv v22, v22, v23 - vadd.vv v27, v20, v22 # t4 + vsub.vv v26, v22, v20 # t3 + vnmsac.vx v21, t3, v3 + vnmsac.vx v23, t5, v5 srli t2, t1, 2 vwadd.vv v8, v28, v24 - vwadd.vv v10, v29, v25 + vwsub.vv v10, v29, v25 + vsub.vv v27, v21, v23 # t4 vwadd.vv v12, v30, v26 vwadd.vv v14, v31, v27 beqz t2, 1f # faster than 4x add t2=zero @@ -174,7 +165,7 @@ func ff_vc1_inv_trans_8_rvv, zve32x 1: vwsub.vv v16, v31, v27 vwsub.vv v18, v30, v26 - vwsub.vv v20, v29, v25 + vwadd.vv v20, v29, v25 vwsub.vv v22, v28, v24 vnclip.wx v0, v8, t1 vnclip.wx v1, v10, t1