diff mbox series

[FFmpeg-devel,2/3] lavc/h264dsp: unroll R-V V weight16

Message ID 20240901161744.102668-2-remi@remlab.net
State New
Headers show
Series [FFmpeg-devel,1/3] lavc/h264dsp: optimise R-V V weight for shorter heights | expand

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Commit Message

Rémi Denis-Courmont Sept. 1, 2024, 4:17 p.m. UTC 
As VLSE128.V does not exist, we have no other way to deal with latency.

T-Head C908:
h264_weight16_8_c:                                     989.4 ( 1.00x)
h264_weight16_8_rvv_i32:                               193.2 ( 5.12x)

SpacemiT X60:
h264_weight16_8_c:                                     874.1 ( 1.00x)
h264_weight16_8_rvv_i32:                               196.9 ( 4.44x)
---
 libavcodec/riscv/h264dsp_init.c |  2 +-
 libavcodec/riscv/h264dsp_rvv.S  | 18 +++++++++++++-----
 2 files changed, 14 insertions(+), 6 deletions(-)
diff mbox series

Patch

diff --git a/libavcodec/riscv/h264dsp_init.c b/libavcodec/riscv/h264dsp_init.c
index 6391667a40..643673d1d6 100644
--- a/libavcodec/riscv/h264dsp_init.c
+++ b/libavcodec/riscv/h264dsp_init.c
@@ -97,7 +97,7 @@  av_cold void ff_h264dsp_init_riscv(H264DSPContext *dsp, const int bit_depth,
         const bool zvl128b = ff_rv_vlen_least(128);
 
         if (bit_depth == 8) {
-            if (zvl128b)
+            if (zvl128b && (flags & AV_CPU_FLAG_RVB))
                 dsp->weight_h264_pixels_tab[0] =
                     ff_h264_weight_funcs_8_rvv[0].weight;
             if (flags & AV_CPU_FLAG_RVV_I64)
diff --git a/libavcodec/riscv/h264dsp_rvv.S b/libavcodec/riscv/h264dsp_rvv.S
index 5c79d1d2b0..9e2f3bc038 100644
--- a/libavcodec/riscv/h264dsp_rvv.S
+++ b/libavcodec/riscv/h264dsp_rvv.S
@@ -29,7 +29,7 @@ 
 #include "libavutil/riscv/asm.S"
 
 .macro  h264_weight depth, w, b=
-func ff_h264_weight_pixels\w\()_\depth\()_rvv, zve64x
+func ff_h264_weight_pixels\w\()_\depth\()_rvv, zve64x, b
         lpad    0
         csrwi   vxrm, 0
         sll     a5, a5, a3
@@ -37,16 +37,24 @@  func ff_h264_weight_pixels\w\()_\depth\()_rvv, zve64x
         li      a6, \w
 1:
         vsetvli     zero, a6, e16, m2, ta, ma
+        add     t0, a0, a1
         vle8.v  v8, (a0)
-        addi    a2, a2, -1
+        addi    a2, a2, -2
+        vle8.v  v9, (t0)
         vzext.vf2   v24, v8
+        vzext.vf2   v26, v9
         vmul.vx     v16, v24, a4
+        vmul.vx     v18, v26, a4
         vsadd.vx    v16, v16, a5
-        vmax.vx v16, v16, zero
-        vsetvli zero, zero, e8, m1, ta, ma
+        vsadd.vx    v18, v18, a5
+        vmax.vx     v16, v16, zero
+        vmax.vx     v18, v18, zero
+        vsetvli     zero, zero, e8, m1, ta, ma
         vnclipu.wx  v8, v16, a3
+        vnclipu.wx  v9, v18, a3
         vse8.v  v8, (a0)
-        add     a0, a0, a1
+        vse8.v  v9, (t0)
+        sh1add  a0, a1, a0
         .else
 1:
         vsetvli     t1, a2, e\b, m2, ta, ma