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[FFmpeg-devel,07/31] lavu/riscv: fallback macros for SH{1, 2, 3}ADD

Message ID 20220925142619.67917-7-remi@remlab.net
State New
Headers show
Series [FFmpeg-devel,01/31] lavu/cpu: detect RISC-V base extensions | expand

Checks

Context Check Description
andriy/make_x86 success Make finished
andriy/make_fate_x86 success Make fate finished

Commit Message

Rémi Denis-Courmont Sept. 25, 2022, 2:25 p.m. UTC 
From: Rémi Denis-Courmont <remi@remlab.net>

Those mnemonics require the very latest binutils release at the time of
writing. These macros provide seamless backward compatibility.
---
 libavutil/riscv/asm.S | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)
diff mbox series

Patch

diff --git a/libavutil/riscv/asm.S b/libavutil/riscv/asm.S
index dbd97f40a4..de5e1ad0a6 100644
--- a/libavutil/riscv/asm.S
+++ b/libavutil/riscv/asm.S
@@ -75,3 +75,22 @@ 
                 .purgem endconst
             .endm
         .endm
+
+#if !defined (__riscv_zba)
+        /* SH{1,2,3}ADD definitions for pre-Zba assemblers */
+        .macro  shnadd n, rd, rs1, rs2
+        .insn r OP, 2 * \n, 16, \rd, \rs1, \rs2
+        .endm
+
+        .macro  sh1add rd, rs1, rs2
+        shnadd  1, \rd, \rs1, \rs2
+        .endm
+
+        .macro  sh2add rd, rs1, rs2
+        shnadd  2, \rd, \rs1, \rs2
+        .endm
+
+        .macro  sh3add rd, rs1, rs2
+        shnadd  3, \rd, \rs1, \rs2
+        .endm
+#endif