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[FFmpeg-devel,1/2] lavc/bswapdsp: rewrite RISC-V V bswap16

Message ID 20230716151352.121105-1-remi@remlab.net
State Accepted
Commit 5de1db53701c470b0d73c521b9385773b97b93f1
Headers show
Series [FFmpeg-devel,1/2] lavc/bswapdsp: rewrite RISC-V V bswap16 | expand

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Commit Message

Rémi Denis-Courmont July 16, 2023, 3:13 p.m. UTC 
This favours bit-wise logic over slow strided stores.
---
 libavcodec/riscv/bswapdsp_rvv.S | 21 ++++++++++-----------
 1 file changed, 10 insertions(+), 11 deletions(-)
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Patch

diff --git a/libavcodec/riscv/bswapdsp_rvv.S b/libavcodec/riscv/bswapdsp_rvv.S
index ef2999c1be..8b585ec5c9 100644
--- a/libavcodec/riscv/bswapdsp_rvv.S
+++ b/libavcodec/riscv/bswapdsp_rvv.S
@@ -45,18 +45,17 @@  func ff_bswap32_buf_rvv, zve32x
 endfunc
 
 func ff_bswap16_buf_rvv, zve32x
-        li      t2, 2
-        addi    t1, a0, 1
 1:
-        vsetvli    t0, a2, e8, m1, ta, ma
-        vlseg2e8.v v8, (a1)
-        sub        a2, a2, t0
-        sh1add     a1, t0, a1
-        vsse8.v    v8, (t1), t2
-        sh1add     t1, t0, t1
-        vsse8.v    v9, (a0), t2
-        sh1add     a0, t0, a0
-        bnez       a2, 1b
+        vsetvli t0, a2, e16, m8, ta, ma
+        vle16.v v8, (a1)
+        sub     a2, a2, t0
+        vsll.vi v16, v8, 8
+        sh1add  a1, t0, a1
+        vsrl.vi v24, v8, 8
+        vor.vv  v8, v16, v24
+        vse16.v v8, (a0)
+        sh1add  a0, t0, a0
+        bnez    a2, 1b
 
         ret
 endfunc