diff mbox series

[FFmpeg-devel,2/3] swscale/rgb2rgb: avoid S-regs in RISC-V V uyvytoyuv422

Message ID 20230930090112.376259-2-remi@remlab.net
State Accepted
Commit e50f8e861ba1390e6ceab7bab591bd3bfa08ced8
Headers show
Series [FFmpeg-devel,1/3] swscale/rgb2rgb: rework RISC-V V uyvytoyuv422 | expand

Checks

Context Check Description
yinshiyou/configure_loongarch64 warning Failed to apply patch
andriy/configure_x86 warning Failed to apply patch

Commit Message

Rémi Denis-Courmont Sept. 30, 2023, 9:01 a.m. UTC 
We can make do with callee-clobbered registers only now.
As an added bonus, this makes the code XLEN-independent.
---
 libswscale/riscv/rgb2rgb.c     |  2 --
 libswscale/riscv/rgb2rgb_rvv.S | 10 ++--------
 2 files changed, 2 insertions(+), 10 deletions(-)
diff mbox series

Patch

diff --git a/libswscale/riscv/rgb2rgb.c b/libswscale/riscv/rgb2rgb.c
index 162a4082b0..565f0b77f1 100644
--- a/libswscale/riscv/rgb2rgb.c
+++ b/libswscale/riscv/rgb2rgb.c
@@ -55,10 +55,8 @@  av_cold void rgb2rgb_init_riscv(void)
         shuffle_bytes_1230 = ff_shuffle_bytes_1230_rvv;
         shuffle_bytes_3012 = ff_shuffle_bytes_3012_rvv;
         interleaveBytes = ff_interleave_bytes_rvv;
-#if (__riscv_xlen == 64)
         uyvytoyuv422 = ff_uyvytoyuv422_rvv;
         yuyvtoyuv422 = ff_yuyvtoyuv422_rvv;
-#endif
     }
 #endif
 }
diff --git a/libswscale/riscv/rgb2rgb_rvv.S b/libswscale/riscv/rgb2rgb_rvv.S
index 3e7988ca01..3200370224 100644
--- a/libswscale/riscv/rgb2rgb_rvv.S
+++ b/libswscale/riscv/rgb2rgb_rvv.S
@@ -100,12 +100,9 @@  func ff_interleave_bytes_rvv, zve32x
         ret
 endfunc
 
-#if (__riscv_xlen == 64)
 .macro yuy2_to_i422p y_shift
-        addi    sp, sp, -16
-        sd      s0,   (sp)
         addi    a4, a4, 1
-        lw      s0, 16(sp)
+        lw      t6, (sp)
         srai    a4, a4, 1 // pixel width -> chroma width
 1:
         mv      t4, a4
@@ -131,14 +128,12 @@  endfunc
         add        t2, t5, t2
         bnez       t4, 2b
 
-        add     a3, a3, s0
+        add     a3, a3, t6
         add     a0, a0, a6
         add     a1, a1, a7
         add     a2, a2, a7
         bnez    a5, 1b
 
-        ld      s0,   (sp)
-        addi    sp, sp, 16
         ret
 .endm
 
@@ -149,4 +144,3 @@  endfunc
 func ff_yuyvtoyuv422_rvv, zve32x
         yuy2_to_i422p 0
 endfunc
-#endif