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[FFmpeg-devel,2/2] lavu/fixed_dsp: R-V V vector_fmul_add

Message ID 20231003201202.121744-2-remi@remlab.net
State New
Headers show
Series [FFmpeg-devel,1/2] lavu/fixed_dsp: R-V V scalarproduct | expand

Checks

Context Check Description
yinshiyou/make_loongarch64 success Make finished
yinshiyou/make_fate_loongarch64 success Make fate finished

Commit Message

Rémi Denis-Courmont Oct. 3, 2023, 8:12 p.m. UTC 
vector_fmul_add_fixed_c: 2.7
vector_fmul_add_fixed_rvv_i64: 0.7
---
 libavutil/riscv/fixed_dsp_init.c |  6 +++++-
 libavutil/riscv/fixed_dsp_rvv.S  | 22 ++++++++++++++++++++++
 2 files changed, 27 insertions(+), 1 deletion(-)
diff mbox series

Patch

diff --git a/libavutil/riscv/fixed_dsp_init.c b/libavutil/riscv/fixed_dsp_init.c
index 409b6d7b55..42e2e69756 100644
--- a/libavutil/riscv/fixed_dsp_init.c
+++ b/libavutil/riscv/fixed_dsp_init.c
@@ -25,6 +25,8 @@ 
 #include "libavutil/cpu.h"
 #include "libavutil/fixed_dsp.h"
 
+void ff_vector_fmul_add_fixed_rvv(int *dst, const int *src0, const int *src1,
+                                  const int *src2, int len);
 int ff_scalarproduct_fixed_rvv(const int *v1, const int *v2, int len);
 void ff_butterflies_fixed_rvv(int *v1, int *v2, int len);
 
@@ -34,8 +36,10 @@  av_cold void ff_fixed_dsp_init_riscv(AVFixedDSPContext *fdsp)
     int flags = av_get_cpu_flags();
 
     if ((flags & AV_CPU_FLAG_RVV_I32) && (flags & AV_CPU_FLAG_RVB_ADDR)) {
-        if (flags & AV_CPU_FLAG_RVV_I64)
+        if (flags & AV_CPU_FLAG_RVV_I64) {
+            fdsp->vector_fmul_add = ff_vector_fmul_add_fixed_rvv;
             fdsp->scalarproduct_fixed = ff_scalarproduct_fixed_rvv;
+        }
         fdsp->butterflies_fixed = ff_butterflies_fixed_rvv;
     }
 #endif
diff --git a/libavutil/riscv/fixed_dsp_rvv.S b/libavutil/riscv/fixed_dsp_rvv.S
index 83cad4bde3..ddff0636e5 100644
--- a/libavutil/riscv/fixed_dsp_rvv.S
+++ b/libavutil/riscv/fixed_dsp_rvv.S
@@ -20,6 +20,28 @@ 
 
 #include "asm.S"
 
+func ff_vector_fmul_add_fixed_rvv, zve64x
+        li      t1, 1 << 30
+1:
+        vsetvli t0, a4, e32, m4, ta, ma
+        vle32.v v16, (a1)
+        sub     a4, a4, t0
+        vle32.v v20, (a2)
+        sh2add  a1, t0, a1
+        vwmul.vv v24, v16, v20
+        vle32.v v12, (a3)
+        sh2add  a2, t0, a2
+        vwadd.wx v24, v24, t1
+        vnsra.wi v8, v24, 31
+        sh2add  a3, t0, a3
+        vadd.vv v8, v12, v8
+        vse32.v v8, (a0)
+        sh2add  a0, t0, a0
+        bnez    a4, 1b
+
+        ret
+endfunc
+
 func ff_scalarproduct_fixed_rvv, zve64x
         li      t1, 1 << 30
         vsetvli t0, zero, e64, m8, ta, ma