diff mbox series

[FFmpeg-devel,3/3] lavc/jpeg2000dsp: R-V V rct_int

Message ID 20231028190455.64807-3-remi@remlab.net
State Accepted
Commit 28840cf499ad0149d690385d8d36666efe15aa95
Headers show
Series [FFmpeg-devel,1/3] lavc/jpeg2000dsp: make coefficients extern | expand

Checks

Context Check Description
andriy/configure_x86 warning Failed to apply patch
yinshiyou/configure_loongarch64 warning Failed to apply patch

Commit Message

Rémi Denis-Courmont Oct. 28, 2023, 7:04 p.m. UTC 
jpeg2000_rct_int_c:       2592.2
jpeg2000_rct_int_rvv_i32: 1154.2
---
 libavcodec/riscv/jpeg2000dsp_init.c |  8 ++++++--
 libavcodec/riscv/jpeg2000dsp_rvv.S  | 23 +++++++++++++++++++++++
 2 files changed, 29 insertions(+), 2 deletions(-)
diff mbox series

Patch

diff --git a/libavcodec/riscv/jpeg2000dsp_init.c b/libavcodec/riscv/jpeg2000dsp_init.c
index 9415a22f79..e82ec47bde 100644
--- a/libavcodec/riscv/jpeg2000dsp_init.c
+++ b/libavcodec/riscv/jpeg2000dsp_init.c
@@ -24,13 +24,17 @@ 
 #include "libavcodec/jpeg2000dsp.h"
 
 void ff_ict_float_rvv(void *src0, void *src1, void *src2, int csize);
+void ff_rct_int_rvv(void *src0, void *src1, void *src2, int csize);
 
 av_cold void ff_jpeg2000dsp_init_riscv(Jpeg2000DSPContext *c)
 {
 #if HAVE_RVV
     int flags = av_get_cpu_flags();
 
-    if ((flags & AV_CPU_FLAG_RVV_F32) && (flags & AV_CPU_FLAG_RVB_ADDR))
-        c->mct_decode[FF_DWT97] = ff_ict_float_rvv;
+    if ((flags & AV_CPU_FLAG_RVV_I32) && (flags & AV_CPU_FLAG_RVB_ADDR)) {
+        if (flags & AV_CPU_FLAG_RVV_F32)
+            c->mct_decode[FF_DWT97] = ff_ict_float_rvv;
+        c->mct_decode[FF_DWT53] = ff_rct_int_rvv;
+    }
 #endif
 }
diff --git a/libavcodec/riscv/jpeg2000dsp_rvv.S b/libavcodec/riscv/jpeg2000dsp_rvv.S
index d10ebd491f..10efe6b0db 100644
--- a/libavcodec/riscv/jpeg2000dsp_rvv.S
+++ b/libavcodec/riscv/jpeg2000dsp_rvv.S
@@ -47,3 +47,26 @@  func ff_ict_float_rvv, zve32f
 
         ret
 endfunc
+
+func ff_rct_int_rvv, zve32x
+1:
+        vsetvli t0, a3, e32, m8, ta, ma
+        vle32.v v16, (a1)
+        sub     a3, a3, t0
+        vle32.v v24, (a2)
+        vle32.v v8, (a0)
+        vadd.vv v0, v16, v24
+        vsra.vi v0, v0, 2
+        vsub.vv v0, v8, v0
+        vadd.vv v8, v0, v24
+        vadd.vv v24, v0, v16
+        vse32.v v8, (a0)
+        sh2add  a0, t0, a0
+        vse32.v v0, (a1)
+        sh2add  a1, t0, a1
+        vse32.v v24, (a2)
+        sh2add  a2, t0, a2
+        bnez    a3, 1b
+
+        ret
+endfunc