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[FFmpeg-devel] lavc/sbrdsp: R-V V sbr_hf_g_filt

Message ID 20231101205247.496993-1-remi@remlab.net
State Accepted
Commit f68ad5d2de40e42b57b9f44ec69d9cbc0f709460
Headers show
Series [FFmpeg-devel] lavc/sbrdsp: R-V V sbr_hf_g_filt | expand

Checks

Context Check Description
yinshiyou/configure_loongarch64 warning Failed to apply patch
andriy/make_x86 success Make finished
andriy/make_fate_x86 success Make fate finished

Commit Message

Rémi Denis-Courmont Nov. 1, 2023, 8:52 p.m. UTC 
hf_g_filt_c:      1552.5
hf_g_filt_rvv_f32: 679.5
---
 libavcodec/riscv/sbrdsp_init.c |  3 +++
 libavcodec/riscv/sbrdsp_rvv.S  | 20 ++++++++++++++++++++
 2 files changed, 23 insertions(+)
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Patch

diff --git a/libavcodec/riscv/sbrdsp_init.c b/libavcodec/riscv/sbrdsp_init.c
index 1b85b2cae9..71de681185 100644
--- a/libavcodec/riscv/sbrdsp_init.c
+++ b/libavcodec/riscv/sbrdsp_init.c
@@ -26,6 +26,8 @@ 
 void ff_sbr_sum64x5_rvv(float *z);
 float ff_sbr_sum_square_rvv(float (*x)[2], int n);
 void ff_sbr_neg_odd_64_rvv(float *x);
+void ff_sbr_hf_g_filt_rvv(float (*Y)[2], const float (*X_high)[40][2],
+                          const float *g_filt, int m_max, intptr_t ixh);
 
 av_cold void ff_sbrdsp_init_riscv(SBRDSPContext *c)
 {
@@ -35,6 +37,7 @@  av_cold void ff_sbrdsp_init_riscv(SBRDSPContext *c)
     if ((flags & AV_CPU_FLAG_RVV_F32) && (flags & AV_CPU_FLAG_RVB_ADDR)) {
         c->sum64x5 = ff_sbr_sum64x5_rvv;
         c->sum_square = ff_sbr_sum_square_rvv;
+        c->hf_g_filt = ff_sbr_hf_g_filt_rvv;
     }
 #if __riscv_xlen >= 64
     if ((flags & AV_CPU_FLAG_RVV_I64) && (flags & AV_CPU_FLAG_RVB_ADDR))
diff --git a/libavcodec/riscv/sbrdsp_rvv.S b/libavcodec/riscv/sbrdsp_rvv.S
index b510190b15..932a5dd7d1 100644
--- a/libavcodec/riscv/sbrdsp_rvv.S
+++ b/libavcodec/riscv/sbrdsp_rvv.S
@@ -84,3 +84,23 @@  func ff_sbr_neg_odd_64_rvv, zve64x
         ret
 endfunc
 #endif
+
+func ff_sbr_hf_g_filt_rvv, zve32f
+        li      t1, 40 * 2 * 4
+        sh3add  a1, a4, a1
+1:
+        vsetvli t0, a3, e32, m4, ta, ma
+        vlsseg2e32.v v16, (a1), t1
+        mul     t2, t0, t1
+        vle32.v v8, (a2)
+        sub     a3, a3, t0
+        vfmul.vv v16, v16, v8
+        add     a1, t2, a1
+        vfmul.vv v20, v20, v8
+        sh2add  a2, t0, a2
+        vsseg2e32.v v16, (a0)
+        sh3add  a0, t0, a0
+        bnez    a3, 1b
+
+        ret
+endfunc