diff mbox series

[FFmpeg-devel,1/2] checkasm/riscv: test misaligned before V

Message ID 20240521175233.31722-1-remi@remlab.net
State Accepted
Commit d03cdfa2b6d7dd42cdaa349ddc11f406a0ffba19
Headers show
Series [FFmpeg-devel,1/2] checkasm/riscv: test misaligned before V | expand

Checks

Context Check Description
yinshiyou/make_loongarch64 success Make finished
yinshiyou/make_fate_loongarch64 success Make fate finished

Commit Message

Rémi Denis-Courmont May 21, 2024, 5:52 p.m. UTC 
Otherwise V functions mask scalar misaligned ones.
---
 tests/checkasm/checkasm.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
diff mbox series

Patch

diff --git a/tests/checkasm/checkasm.c b/tests/checkasm/checkasm.c
index 31ca9f6e2b..76835ab267 100644
--- a/tests/checkasm/checkasm.c
+++ b/tests/checkasm/checkasm.c
@@ -278,6 +278,7 @@  static const struct {
     { "POWER8",   "power8",   AV_CPU_FLAG_POWER8 },
 #elif ARCH_RISCV
     { "RVI",      "rvi",      AV_CPU_FLAG_RVI },
+    { "misaligned", "misaligned", AV_CPU_FLAG_RV_MISALIGNED },
     { "RVF",      "rvf",      AV_CPU_FLAG_RVF },
     { "RVD",      "rvd",      AV_CPU_FLAG_RVD },
     { "RVBaddr",  "rvb_a",    AV_CPU_FLAG_RVB_ADDR },
@@ -287,7 +288,6 @@  static const struct {
     { "RVVi64",   "rvv_i64",  AV_CPU_FLAG_RVV_I64 },
     { "RVVf64",   "rvv_f64",  AV_CPU_FLAG_RVV_F64 },
     { "RV_Zvbb",  "rv_zvbb",  AV_CPU_FLAG_RV_ZVBB },
-    { "misaligned", "misaligned", AV_CPU_FLAG_RV_MISALIGNED },
 #elif ARCH_MIPS
     { "MMI",      "mmi",      AV_CPU_FLAG_MMI },
     { "MSA",      "msa",      AV_CPU_FLAG_MSA },