diff mbox series

[FFmpeg-devel,4/5] x86/vvc_sad: reduce gpr usage in all loop functions

Message ID 20240523122716.2158-4-jamrial@gmail.com
State New
Headers show
Series [FFmpeg-devel,1/5] avcodec/vvc_mc: split the SAD dsp prototype into one function per blocksize width | expand

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Context Check Description
yinshiyou/make_loongarch64 success Make finished
yinshiyou/make_fate_loongarch64 success Make fate finished
andriy/make_x86 success Make finished
andriy/make_fate_x86 success Make fate finished

Commit Message

James Almer May 23, 2024, 12:27 p.m. UTC 
This way they can be assembled on x86_32 targets.

Signed-off-by: James Almer <jamrial@gmail.com>
---
 libavcodec/x86/vvc/vvc_sad.asm   | 22 ++++++++++------------
 libavcodec/x86/vvc/vvcdsp_init.c | 16 +++++++++++++---
 2 files changed, 23 insertions(+), 15 deletions(-)
diff mbox series

Patch

diff --git a/libavcodec/x86/vvc/vvc_sad.asm b/libavcodec/x86/vvc/vvc_sad.asm
index 26df25ec66..9881b1180d 100644
--- a/libavcodec/x86/vvc/vvc_sad.asm
+++ b/libavcodec/x86/vvc/vvc_sad.asm
@@ -49,7 +49,7 @@  SECTION .text
 %endmacro
 
 %macro VVC_SAD 1
-cglobal vvc_sad_%1, 4, 7, 5, src1, src2, dx, dy, off1, block_h, off2
+cglobal vvc_sad_%1, 4, 6, 5, src1, src2, dx, dy, off, block_h
 %if UNIX64 == 0
     mov             block_hd, dword r5m
 %endif
@@ -59,12 +59,12 @@  cglobal vvc_sad_%1, 4, 7, 5, src1, src2, dx, dy, off1, block_h, off2
     sub             dxq, 2
     sub             dyq, 2
 
-    mov             off1q, 2
-    mov             off2q, 2
+    mov             offq, 2
 
-    add             off1q, dyq
-    sub             off2q, dyq
+    sub             offq, dyq
+    add             dyq, 2
 
+DEFINE_ARGS src1, src2, dx, off1, off2, block_h
     shl             off1q, 7
     shl             off2q, 7
 
@@ -100,19 +100,19 @@  cglobal vvc_sad_%1, 4, 7, 5, src1, src2, dx, dy, off1, block_h, off2
 %endmacro
 
 %macro VVC_SAD_LOOP 1
-cglobal vvc_sad_%1, 6, 8, 5, src1, src2, dx, dy, block_w, block_h, off1, off2
+cglobal vvc_sad_%1, 6, 7, 5, src1, src2, dx, dy, block_w, block_h, off
     movsxdifnidn    dxq, dxd
     movsxdifnidn    dyq, dyd
 
     sub             dxq, 2
     sub             dyq, 2
 
-    mov             off1q, 2
-    mov             off2q, 2
+    mov             offq, 2
 
-    add             off1q, dyq
-    sub             off2q, dyq
+    sub             offq, dyq
+    add             dyq, 2
 
+DEFINE_ARGS src1, src2, dx, off1, block_w, block_h, off2
     shl             off1q, 7
     shl             off2q, 7
 
@@ -159,7 +159,6 @@  DEFINE_ARGS src1, src2, dx, dy, block_w, block_h, row_idx
     RET
 %endmacro
 
-%if ARCH_X86_64
 INIT_XMM sse4
 VVC_SAD 8
 VVC_SAD_LOOP 16
@@ -168,4 +167,3 @@  INIT_YMM avx2
 VVC_SAD 16
 VVC_SAD_LOOP 32
 %endif
-%endif
diff --git a/libavcodec/x86/vvc/vvcdsp_init.c b/libavcodec/x86/vvc/vvcdsp_init.c
index cdf0e36b62..c0bd145191 100644
--- a/libavcodec/x86/vvc/vvcdsp_init.c
+++ b/libavcodec/x86/vvc/vvcdsp_init.c
@@ -311,6 +311,7 @@  ALF_FUNCS(16, 12, avx2)
     c->alf.filter[CHROMA] = ff_vvc_alf_filter_chroma_##bd##_avx2;    \
     c->alf.classify       = ff_vvc_alf_classify_##bd##_avx2;         \
 } while (0)
+#endif
 
 #define SAD_PROTOTYPE(w, opt)                                        \
 int bf(ff_vvc_sad, w, opt)(const int16_t *src0, const int16_t *src1, \
@@ -320,17 +321,17 @@  SAD_PROTOTYPE(8,   sse4);
 SAD_PROTOTYPE(16,  sse4);
 SAD_PROTOTYPE(16,  avx2);
 SAD_PROTOTYPE(32,  avx2);
-#endif
 
 void ff_vvc_dsp_init_x86(VVCDSPContext *const c, const int bd)
 {
-#if ARCH_X86_64
     const int cpu_flags = av_get_cpu_flags();
 
     switch (bd) {
     case 8:
         if (EXTERNAL_SSE4(cpu_flags)) {
+#if ARCH_X86_64
             MC_LINK_SSE4(8);
+#endif
             c->inter.sad[0] = ff_vvc_sad_8_sse4;
             c->inter.sad[1] =
             c->inter.sad[2] =
@@ -338,9 +339,11 @@  void ff_vvc_dsp_init_x86(VVCDSPContext *const c, const int bd)
             c->inter.sad[4] = ff_vvc_sad_16_sse4;
         }
         if (EXTERNAL_AVX2_FAST(cpu_flags)) {
+#if ARCH_X86_64
             ALF_INIT(8);
             AVG_INIT(8, avx2);
             MC_LINKS_AVX2(8);
+#endif
             c->inter.sad[1] = ff_vvc_sad_16_avx2;
             c->inter.sad[2] =
             c->inter.sad[3] =
@@ -349,7 +352,9 @@  void ff_vvc_dsp_init_x86(VVCDSPContext *const c, const int bd)
         break;
     case 10:
         if (EXTERNAL_SSE4(cpu_flags)) {
+#if ARCH_X86_64
             MC_LINK_SSE4(10);
+#endif
             c->inter.sad[0] = ff_vvc_sad_8_sse4;
             c->inter.sad[1] =
             c->inter.sad[2] =
@@ -357,10 +362,12 @@  void ff_vvc_dsp_init_x86(VVCDSPContext *const c, const int bd)
             c->inter.sad[4] = ff_vvc_sad_16_sse4;
         }
         if (EXTERNAL_AVX2_FAST(cpu_flags)) {
+#if ARCH_X86_64
             ALF_INIT(10);
             AVG_INIT(10, avx2);
             MC_LINKS_AVX2(10);
             MC_LINKS_16BPC_AVX2(10);
+#endif
             c->inter.sad[1] = ff_vvc_sad_16_avx2;
             c->inter.sad[2] =
             c->inter.sad[3] =
@@ -369,7 +376,9 @@  void ff_vvc_dsp_init_x86(VVCDSPContext *const c, const int bd)
         break;
     case 12:
         if (EXTERNAL_SSE4(cpu_flags)) {
+#if ARCH_X86_64
             MC_LINK_SSE4(12);
+#endif
             c->inter.sad[0] = ff_vvc_sad_8_sse4;
             c->inter.sad[1] =
             c->inter.sad[2] =
@@ -377,10 +386,12 @@  void ff_vvc_dsp_init_x86(VVCDSPContext *const c, const int bd)
             c->inter.sad[4] = ff_vvc_sad_16_sse4;
         }
         if (EXTERNAL_AVX2_FAST(cpu_flags)) {
+#if ARCH_X86_64
             ALF_INIT(12);
             AVG_INIT(12, avx2);
             MC_LINKS_AVX2(12);
             MC_LINKS_16BPC_AVX2(12);
+#endif
             c->inter.sad[1] = ff_vvc_sad_16_avx2;
             c->inter.sad[2] =
             c->inter.sad[3] =
@@ -390,5 +401,4 @@  void ff_vvc_dsp_init_x86(VVCDSPContext *const c, const int bd)
     default:
         break;
     }
-#endif
 }