Message ID | 20240722184431.40853-7-remi@remlab.net |
---|---|
State | New |
Headers | show |
Series | [FFmpeg-devel,1/9] lavu/riscv: allow any number of extensions | expand |
Context | Check | Description |
---|---|---|
andriy/make_x86 | success | Make finished |
andriy/make_fate_x86 | success | Make fate finished |
diff --git a/libavutil/riscv/asm.S b/libavutil/riscv/asm.S index 0c29680d84..8b96e07b75 100644 --- a/libavutil/riscv/asm.S +++ b/libavutil/riscv/asm.S @@ -83,25 +83,6 @@ .endm .endm -#if !defined (__riscv_zba) - /* SH{1,2,3}ADD definitions for pre-Zba assemblers */ - .macro shnadd n, rd, rs1, rs2 - .insn r OP, 2 * \n, 16, \rd, \rs1, \rs2 - .endm - - .macro sh1add rd, rs1, rs2 - shnadd 1, \rd, \rs1, \rs2 - .endm - - .macro sh2add rd, rs1, rs2 - shnadd 2, \rd, \rs1, \rs2 - .endm - - .macro sh3add rd, rs1, rs2 - shnadd 3, \rd, \rs1, \rs2 - .endm -#endif - #if defined (__riscv_v_elen) # define RV_V_ELEN __riscv_v_elen #else