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[FFmpeg-devel,1/6] lavu/riscv: assembly for zicfilp LPAD

Message ID 20240722193818.50824-1-remi@remlab.net
State New
Headers show
Series [FFmpeg-devel,1/6] lavu/riscv: assembly for zicfilp LPAD | expand

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Context Check Description
andriy/make_x86 success Make finished
andriy/make_fate_x86 success Make fate finished

Commit Message

Rémi Denis-Courmont July 22, 2024, 7:38 p.m. UTC
This instruction, if aligned on a 4-byte boundary, defines a valid target
("landing pad") for an indirect call or jump. Since this instruction is a
HINT, it is safe to assemble even if not included in the target
instruction set architecture.

The necessary alignment is already provided by the `func` macro. However
this still lacks the ELF attribute to indicate that the zicfilp is supported
in simple mode. This is left for future work as the ELF specification is not
ratified as of yet.

This will also nonobviously require the assembler to support zicfilp,
insofar as the `tail` pseudo-instruction shall clobber T2 (instead of T1) as
its temporary register.
---
 libavutil/riscv/asm.S | 6 ++++++
 1 file changed, 6 insertions(+)
diff mbox series

Patch

diff --git a/libavutil/riscv/asm.S b/libavutil/riscv/asm.S
index 2cf4f7b7ab..37fd7d3b03 100644
--- a/libavutil/riscv/asm.S
+++ b/libavutil/riscv/asm.S
@@ -77,6 +77,12 @@ 
             .endm
         .endm
 
+#if !defined (__riscv_zicfilp)
+        .macro  lpad    lpl
+        auipc   zero, \lpl
+        .endm
+#endif
+
 #if !defined (__riscv_zba)
         /* SH{1,2,3}ADD definitions for pre-Zba assemblers */
         .macro  shnadd n, rd, rs1, rs2