diff mbox series

[FFmpeg-devel,5/6] lavc/riscv: drop probing for F & D extensions

Message ID 20240725202522.276182-5-remi@remlab.net
State New
Headers show
Series [FFmpeg-devel,1/6] lavu/riscv: implement floating point clips | expand

Checks

Context Check Description
andriy/make_x86 success Make finished
andriy/make_fate_x86 success Make fate finished

Commit Message

Rémi Denis-Courmont July 25, 2024, 8:25 p.m. UTC 
F and D extensions are included in all RISC-V application profiles ever
made (so starting from RV64GC a.k.a. RVA20). Realistically they need to be
selected at compilation time.

Currently, there are no consumers for these two flags. If there is ever a
need to reintroduce F- or D-specific optimisations, we can always use
__riscv_f or __riscv_d compiler predefined macros respectively.
---
 libavutil/cpu.c           |  2 --
 libavutil/riscv/cpu.c     | 12 ------------
 libavutil/tests/cpu.c     |  2 --
 tests/checkasm/checkasm.c |  2 --
 4 files changed, 18 deletions(-)
diff mbox series

Patch

diff --git a/libavutil/cpu.c b/libavutil/cpu.c
index 17afe8858a..6c26182b78 100644
--- a/libavutil/cpu.c
+++ b/libavutil/cpu.c
@@ -184,8 +184,6 @@  int av_parse_cpu_caps(unsigned *flags, const char *s)
         { "lasx",     NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_LASX     },    .unit = "flags" },
 #elif ARCH_RISCV
         { "rvi",      NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_RVI      },    .unit = "flags" },
-        { "rvf",      NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_RVF      },    .unit = "flags" },
-        { "rvd",      NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_RVD      },    .unit = "flags" },
         { "rvb",      NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_RVB      },    .unit = "flags" },
         { "zve32x",   NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_RVV_I32  },    .unit = "flags" },
         { "zve32f",   NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_RVV_F32  },    .unit = "flags" },
diff --git a/libavutil/riscv/cpu.c b/libavutil/riscv/cpu.c
index e035f4b024..6537e91965 100644
--- a/libavutil/riscv/cpu.c
+++ b/libavutil/riscv/cpu.c
@@ -58,8 +58,6 @@  int ff_get_cpu_flags_riscv(void)
     if (__riscv_hwprobe(pairs, FF_ARRAY_ELEMS(pairs), 0, NULL, 0) == 0) {
         if (pairs[0].value & RISCV_HWPROBE_BASE_BEHAVIOR_IMA)
             ret |= AV_CPU_FLAG_RVI;
-        if (pairs[1].value & RISCV_HWPROBE_IMA_FD)
-            ret |= AV_CPU_FLAG_RVF | AV_CPU_FLAG_RVD;
 #ifdef RISCV_HWPROBE_IMA_V
         if (pairs[1].value & RISCV_HWPROBE_IMA_V)
             ret |= AV_CPU_FLAG_RVV_I32 | AV_CPU_FLAG_RVV_I64
@@ -96,10 +94,6 @@  int ff_get_cpu_flags_riscv(void)
 
         if (hwcap & HWCAP_RV('I'))
             ret |= AV_CPU_FLAG_RVI;
-        if (hwcap & HWCAP_RV('F'))
-            ret |= AV_CPU_FLAG_RVF;
-        if (hwcap & HWCAP_RV('D'))
-            ret |= AV_CPU_FLAG_RVD;
         if (hwcap & HWCAP_RV('B'))
             ret |= AV_CPU_FLAG_RVB_ADDR | AV_CPU_FLAG_RVB_BASIC |
                    AV_CPU_FLAG_RVB;
@@ -114,12 +108,6 @@  int ff_get_cpu_flags_riscv(void)
 #ifdef __riscv_i
     ret |= AV_CPU_FLAG_RVI;
 #endif
-#if defined (__riscv_flen) && (__riscv_flen >= 32)
-    ret |= AV_CPU_FLAG_RVF;
-#if (__riscv_flen >= 64)
-    ret |= AV_CPU_FLAG_RVD;
-#endif
-#endif
 
 #ifdef __riscv_zba
     ret |= AV_CPU_FLAG_RVB_ADDR;
diff --git a/libavutil/tests/cpu.c b/libavutil/tests/cpu.c
index b4b11775d8..e03fbf94eb 100644
--- a/libavutil/tests/cpu.c
+++ b/libavutil/tests/cpu.c
@@ -86,8 +86,6 @@  static const struct {
     { AV_CPU_FLAG_LASX,      "lasx"       },
 #elif ARCH_RISCV
     { AV_CPU_FLAG_RVI,       "rvi"        },
-    { AV_CPU_FLAG_RVF,       "rvf"        },
-    { AV_CPU_FLAG_RVD,       "rvd"        },
     { AV_CPU_FLAG_RVB_ADDR,  "zba"        },
     { AV_CPU_FLAG_RVB_BASIC, "zbb"        },
     { AV_CPU_FLAG_RVB,       "rvb"        },
diff --git a/tests/checkasm/checkasm.c b/tests/checkasm/checkasm.c
index 016f2329b0..49b47f8615 100644
--- a/tests/checkasm/checkasm.c
+++ b/tests/checkasm/checkasm.c
@@ -291,8 +291,6 @@  static const struct {
 #elif ARCH_RISCV
     { "RVI",      "rvi",      AV_CPU_FLAG_RVI },
     { "misaligned", "misaligned", AV_CPU_FLAG_RV_MISALIGNED },
-    { "RVF",      "rvf",      AV_CPU_FLAG_RVF },
-    { "RVD",      "rvd",      AV_CPU_FLAG_RVD },
     { "RVBaddr",  "rvb_a",    AV_CPU_FLAG_RVB_ADDR },
     { "RVBbasic", "rvb_b",    AV_CPU_FLAG_RVB_BASIC },
     { "RVB",      "rvb",      AV_CPU_FLAG_RVB },