[FFmpeg-devel,04/16] avutil: add hardware definitions for NVDEC, NVJPG and VIC

Message ID	60ec1bcddd512652c74798236ce7f5f5178ae20c.1717083799.git.averne381@gmail.com
State	New
Headers	show Delivered-To: ffmpegpatchwork2@gmail.com Received-SPF: pass (google.com: domain of ffmpeg-devel-bounces@ffmpeg.org designates 79.124.17.100 as permitted sender) client-ip=79.124.17.100; From: averne <averne381@gmail.com> To: ffmpeg-devel@ffmpeg.org Date: Thu, 30 May 2024 21:43:06 +0200 Message-ID: <60ec1bcddd512652c74798236ce7f5f5178ae20c.1717083799.git.averne381@gmail.com> In-Reply-To: <cover.1717083799.git.averne381@gmail.com> References: <cover.1717083799.git.averne381@gmail.com> MIME-Version: 1.0 Subject: [FFmpeg-devel] [PATCH 04/16] avutil: add hardware definitions for NVDEC, NVJPG and VIC Precedence: list Reply-To: FFmpeg development discussions and patches <ffmpeg-devel@ffmpeg.org> Cc: averne <averne381@gmail.com> Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: ffmpeg-devel-bounces@ffmpeg.org Sender: "ffmpeg-devel" <ffmpeg-devel-bounces@ffmpeg.org>
Series	NVidia Tegra hardware decoding backend \| expand [FFmpeg-devel,00/16] NVidia Tegra hardware decoding backend [FFmpeg-devel,01/16] avutil/buffer: add helper to allocate aligned memory [FFmpeg-devel,02/16] configure, avutil: add support for HorizonOS [FFmpeg-devel,03/16] avutil: add ioctl definitions for tegra devices [FFmpeg-devel,04/16] avutil: add hardware definitions for NVDEC, NVJPG and VIC [FFmpeg-devel,05/16] avutil: add common code for nvtegra [FFmpeg-devel,06/16] avutil: add nvtegra hwcontext [FFmpeg-devel,07/16] hwcontext_nvtegra: add dynamic frequency scaling routines [FFmpeg-devel,08/16] nvtegra: add common hardware decoding code [FFmpeg-devel,09/16] nvtegra: add mpeg1/2 hardware decoding [FFmpeg-devel,10/16] nvtegra: add mpeg4 hardware decoding [FFmpeg-devel,11/16] nvtegra: add vc1 hardware decoding [FFmpeg-devel,12/16] nvtegra: add h264 hardware decoding [FFmpeg-devel,13/16] nvtegra: add hevc hardware decoding [FFmpeg-devel,14/16] nvtegra: add vp8 hardware decoding [FFmpeg-devel,15/16] nvtegra: add vp9 hardware decoding [FFmpeg-devel,16/16] nvtegra: add mjpeg hardware decoding

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diff --git a/libavutil/clb0b6.h b/libavutil/clb0b6.h new file mode 100644 index 0000000000..ee81ebc9d8 --- /dev/null +++ b/libavutil/clb0b6.h @@ -0,0 +1,303 @@ +/* + * Copyright (c) 2024 averne <averne381@gmail.com> + * + * This file is part of FFmpeg. + * + * FFmpeg is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * FFmpeg is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with FFmpeg; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef AVUTIL_CLB0B6_H +#define AVUTIL_CLB0B6_H + +#ifdef __cplusplus +extern "C" { +#endif + +#define NVB0B6_VIDEO_COMPOSITOR (0x0000B0B6) + +#define NVB0B6_VIDEO_COMPOSITOR_NOP (0x00000100) +#define NVB0B6_VIDEO_COMPOSITOR_NOP_PARAMETER 31:0 +#define NVB0B6_VIDEO_COMPOSITOR_PM_TRIGGER (0x00000140) +#define NVB0B6_VIDEO_COMPOSITOR_PM_TRIGGER_V 31:0 +#define NVB0B6_VIDEO_COMPOSITOR_SET_APPLICATION_ID (0x00000200) +#define NVB0B6_VIDEO_COMPOSITOR_SET_APPLICATION_ID_ID 31:0 +#define NVB0B6_VIDEO_COMPOSITOR_SET_APPLICATION_ID_ID_COMPOSITOR (0x00000000) +#define NVB0B6_VIDEO_COMPOSITOR_SET_WATCHDOG_TIMER (0x00000204) +#define NVB0B6_VIDEO_COMPOSITOR_SET_WATCHDOG_TIMER_TIMER 31:0 +#define NVB0B6_VIDEO_COMPOSITOR_SEMAPHORE_A (0x00000240) +#define NVB0B6_VIDEO_COMPOSITOR_SEMAPHORE_A_UPPER 7:0 +#define NVB0B6_VIDEO_COMPOSITOR_SEMAPHORE_B (0x00000244) +#define NVB0B6_VIDEO_COMPOSITOR_SEMAPHORE_B_LOWER 31:0 +#define NVB0B6_VIDEO_COMPOSITOR_SEMAPHORE_C (0x00000248) +#define NVB0B6_VIDEO_COMPOSITOR_SEMAPHORE_C_PAYLOAD 31:0 +#define NVB0B6_VIDEO_COMPOSITOR_CTX_SAVE_AREA (0x0000024C) +#define NVB0B6_VIDEO_COMPOSITOR_CTX_SAVE_AREA_OFFSET 27:0 +#define NVB0B6_VIDEO_COMPOSITOR_CTX_SAVE_AREA_CTX_VALID 31:28 +#define NVB0B6_VIDEO_COMPOSITOR_CTX_SWITCH (0x00000250) +#define NVB0B6_VIDEO_COMPOSITOR_CTX_SWITCH_RESTORE 0:0 +#define NVB0B6_VIDEO_COMPOSITOR_CTX_SWITCH_RESTORE_FALSE (0x00000000) +#define NVB0B6_VIDEO_COMPOSITOR_CTX_SWITCH_RESTORE_TRUE (0x00000001) +#define NVB0B6_VIDEO_COMPOSITOR_CTX_SWITCH_RST_NOTIFY 1:1 +#define NVB0B6_VIDEO_COMPOSITOR_CTX_SWITCH_RST_NOTIFY_FALSE (0x00000000) +#define NVB0B6_VIDEO_COMPOSITOR_CTX_SWITCH_RST_NOTIFY_TRUE (0x00000001) +#define NVB0B6_VIDEO_COMPOSITOR_CTX_SWITCH_RESERVED 7:2 +#define NVB0B6_VIDEO_COMPOSITOR_CTX_SWITCH_ASID 23:8 +#define NVB0B6_VIDEO_COMPOSITOR_EXECUTE (0x00000300) +#define NVB0B6_VIDEO_COMPOSITOR_EXECUTE_NOTIFY 0:0 +#define NVB0B6_VIDEO_COMPOSITOR_EXECUTE_NOTIFY_DISABLE (0x00000000) +#define NVB0B6_VIDEO_COMPOSITOR_EXECUTE_NOTIFY_ENABLE (0x00000001) +#define NVB0B6_VIDEO_COMPOSITOR_EXECUTE_NOTIFY_ON 1:1 +#define NVB0B6_VIDEO_COMPOSITOR_EXECUTE_NOTIFY_ON_END (0x00000000) +#define NVB0B6_VIDEO_COMPOSITOR_EXECUTE_NOTIFY_ON_BEGIN (0x00000001) +#define NVB0B6_VIDEO_COMPOSITOR_EXECUTE_AWAKEN 8:8 +#define NVB0B6_VIDEO_COMPOSITOR_EXECUTE_AWAKEN_DISABLE (0x00000000) +#define NVB0B6_VIDEO_COMPOSITOR_EXECUTE_AWAKEN_ENABLE (0x00000001) +#define NVB0B6_VIDEO_COMPOSITOR_SEMAPHORE_D (0x00000304) +#define NVB0B6_VIDEO_COMPOSITOR_SEMAPHORE_D_STRUCTURE_SIZE 0:0 +#define NVB0B6_VIDEO_COMPOSITOR_SEMAPHORE_D_STRUCTURE_SIZE_ONE (0x00000000) +#define NVB0B6_VIDEO_COMPOSITOR_SEMAPHORE_D_STRUCTURE_SIZE_FOUR (0x00000001) +#define NVB0B6_VIDEO_COMPOSITOR_SEMAPHORE_D_AWAKEN_ENABLE 8:8 +#define NVB0B6_VIDEO_COMPOSITOR_SEMAPHORE_D_AWAKEN_ENABLE_FALSE (0x00000000) +#define NVB0B6_VIDEO_COMPOSITOR_SEMAPHORE_D_AWAKEN_ENABLE_TRUE (0x00000001) +#define NVB0B6_VIDEO_COMPOSITOR_SEMAPHORE_D_OPERATION 17:16 +#define NVB0B6_VIDEO_COMPOSITOR_SEMAPHORE_D_OPERATION_RELEASE (0x00000000) +#define NVB0B6_VIDEO_COMPOSITOR_SEMAPHORE_D_OPERATION_RESERVED0 (0x00000001) +#define NVB0B6_VIDEO_COMPOSITOR_SEMAPHORE_D_OPERATION_RESERVED1 (0x00000002) +#define NVB0B6_VIDEO_COMPOSITOR_SEMAPHORE_D_OPERATION_TRAP (0x00000003) +#define NVB0B6_VIDEO_COMPOSITOR_SEMAPHORE_D_FLUSH_DISABLE 21:21 +#define NVB0B6_VIDEO_COMPOSITOR_SEMAPHORE_D_FLUSH_DISABLE_FALSE (0x00000000) +#define NVB0B6_VIDEO_COMPOSITOR_SEMAPHORE_D_FLUSH_DISABLE_TRUE (0x00000001) +#define NVB0B6_VIDEO_COMPOSITOR_SET_SURFACE0_LUMA_OFFSET(b) (0x00000400 + (b)*0x00000060) +#define NVB0B6_VIDEO_COMPOSITOR_SET_SURFACE0_LUMA_OFFSET_OFFSET 31:0 +#define NVB0B6_VIDEO_COMPOSITOR_SET_SURFACE0_CHROMA_U_OFFSET(b) (0x00000404 + (b)*0x00000060) +#define NVB0B6_VIDEO_COMPOSITOR_SET_SURFACE0_CHROMA_U_OFFSET_OFFSET 31:0 +#define NVB0B6_VIDEO_COMPOSITOR_SET_SURFACE0_CHROMA_V_OFFSET(b) (0x00000408 + (b)*0x00000060) +#define NVB0B6_VIDEO_COMPOSITOR_SET_SURFACE0_CHROMA_V_OFFSET_OFFSET 31:0 +#define NVB0B6_VIDEO_COMPOSITOR_SET_SURFACE1_LUMA_OFFSET(b) (0x0000040C + (b)*0x00000060) +#define NVB0B6_VIDEO_COMPOSITOR_SET_SURFACE1_LUMA_OFFSET_OFFSET 31:0 +#define NVB0B6_VIDEO_COMPOSITOR_SET_SURFACE1_CHROMA_U_OFFSET(b) (0x00000410 + (b)*0x00000060) +#define NVB0B6_VIDEO_COMPOSITOR_SET_SURFACE1_CHROMA_U_OFFSET_OFFSET 31:0 +#define NVB0B6_VIDEO_COMPOSITOR_SET_SURFACE1_CHROMA_V_OFFSET(b) (0x00000414 + (b)*0x00000060) +#define NVB0B6_VIDEO_COMPOSITOR_SET_SURFACE1_CHROMA_V_OFFSET_OFFSET 31:0 +#define NVB0B6_VIDEO_COMPOSITOR_SET_SURFACE2_LUMA_OFFSET(b) (0x00000418 + (b)*0x00000060) +#define NVB0B6_VIDEO_COMPOSITOR_SET_SURFACE2_LUMA_OFFSET_OFFSET 31:0 +#define NVB0B6_VIDEO_COMPOSITOR_SET_SURFACE2_CHROMA_U_OFFSET(b) (0x0000041C + (b)*0x00000060) +#define NVB0B6_VIDEO_COMPOSITOR_SET_SURFACE2_CHROMA_U_OFFSET_OFFSET 31:0 +#define NVB0B6_VIDEO_COMPOSITOR_SET_SURFACE2_CHROMA_V_OFFSET(b) (0x00000420 + (b)*0x00000060) +#define NVB0B6_VIDEO_COMPOSITOR_SET_SURFACE2_CHROMA_V_OFFSET_OFFSET 31:0 +#define NVB0B6_VIDEO_COMPOSITOR_SET_SURFACE3_LUMA_OFFSET(b) (0x00000424 + (b)*0x00000060) +#define NVB0B6_VIDEO_COMPOSITOR_SET_SURFACE3_LUMA_OFFSET_OFFSET 31:0 +#define NVB0B6_VIDEO_COMPOSITOR_SET_SURFACE3_CHROMA_U_OFFSET(b) (0x00000428 + (b)*0x00000060) +#define NVB0B6_VIDEO_COMPOSITOR_SET_SURFACE3_CHROMA_U_OFFSET_OFFSET 31:0 +#define NVB0B6_VIDEO_COMPOSITOR_SET_SURFACE3_CHROMA_V_OFFSET(b) (0x0000042C + (b)*0x00000060) +#define NVB0B6_VIDEO_COMPOSITOR_SET_SURFACE3_CHROMA_V_OFFSET_OFFSET 31:0 +#define NVB0B6_VIDEO_COMPOSITOR_SET_SURFACE4_LUMA_OFFSET(b) (0x00000430 + (b)*0x00000060) +#define NVB0B6_VIDEO_COMPOSITOR_SET_SURFACE4_LUMA_OFFSET_OFFSET 31:0 +#define NVB0B6_VIDEO_COMPOSITOR_SET_SURFACE4_CHROMA_U_OFFSET(b) (0x00000434 + (b)*0x00000060) +#define NVB0B6_VIDEO_COMPOSITOR_SET_SURFACE4_CHROMA_U_OFFSET_OFFSET 31:0 +#define NVB0B6_VIDEO_COMPOSITOR_SET_SURFACE4_CHROMA_V_OFFSET(b) (0x00000438 + (b)*0x00000060) +#define NVB0B6_VIDEO_COMPOSITOR_SET_SURFACE4_CHROMA_V_OFFSET_OFFSET 31:0 +#define NVB0B6_VIDEO_COMPOSITOR_SET_SURFACE5_LUMA_OFFSET(b) (0x0000043C + (b)*0x00000060) +#define NVB0B6_VIDEO_COMPOSITOR_SET_SURFACE5_LUMA_OFFSET_OFFSET 31:0 +#define NVB0B6_VIDEO_COMPOSITOR_SET_SURFACE5_CHROMA_U_OFFSET(b) (0x00000440 + (b)*0x00000060) +#define NVB0B6_VIDEO_COMPOSITOR_SET_SURFACE5_CHROMA_U_OFFSET_OFFSET 31:0 +#define NVB0B6_VIDEO_COMPOSITOR_SET_SURFACE5_CHROMA_V_OFFSET(b) (0x00000444 + (b)*0x00000060) +#define NVB0B6_VIDEO_COMPOSITOR_SET_SURFACE5_CHROMA_V_OFFSET_OFFSET 31:0 +#define NVB0B6_VIDEO_COMPOSITOR_SET_SURFACE6_LUMA_OFFSET(b) (0x00000448 + (b)*0x00000060) +#define NVB0B6_VIDEO_COMPOSITOR_SET_SURFACE6_LUMA_OFFSET_OFFSET 31:0 +#define NVB0B6_VIDEO_COMPOSITOR_SET_SURFACE6_CHROMA_U_OFFSET(b) (0x0000044C + (b)*0x00000060) +#define NVB0B6_VIDEO_COMPOSITOR_SET_SURFACE6_CHROMA_U_OFFSET_OFFSET 31:0 +#define NVB0B6_VIDEO_COMPOSITOR_SET_SURFACE6_CHROMA_V_OFFSET(b) (0x00000450 + (b)*0x00000060) +#define NVB0B6_VIDEO_COMPOSITOR_SET_SURFACE6_CHROMA_V_OFFSET_OFFSET 31:0 +#define NVB0B6_VIDEO_COMPOSITOR_SET_SURFACE7_LUMA_OFFSET(b) (0x00000454 + (b)*0x00000060) +#define NVB0B6_VIDEO_COMPOSITOR_SET_SURFACE7_LUMA_OFFSET_OFFSET 31:0 +#define NVB0B6_VIDEO_COMPOSITOR_SET_SURFACE7_CHROMA_U_OFFSET(b) (0x00000458 + (b)*0x00000060) +#define NVB0B6_VIDEO_COMPOSITOR_SET_SURFACE7_CHROMA_U_OFFSET_OFFSET 31:0 +#define NVB0B6_VIDEO_COMPOSITOR_SET_SURFACE7_CHROMA_V_OFFSET(b) (0x0000045C + (b)*0x00000060) +#define NVB0B6_VIDEO_COMPOSITOR_SET_SURFACE7_CHROMA_V_OFFSET_OFFSET 31:0 +#define NVB0B6_VIDEO_COMPOSITOR_SET_PICTURE_INDEX (0x00000700) +#define NVB0B6_VIDEO_COMPOSITOR_SET_PICTURE_INDEX_INDEX 31:0 +#define NVB0B6_VIDEO_COMPOSITOR_SET_CONTROL_PARAMS (0x00000704) +#define NVB0B6_VIDEO_COMPOSITOR_SET_CONTROL_PARAMS_GPTIMER_ON 0:0 +#define NVB0B6_VIDEO_COMPOSITOR_SET_CONTROL_PARAMS_DEBUG_MODE 4:4 +#define NVB0B6_VIDEO_COMPOSITOR_SET_CONTROL_PARAMS_FALCON_CONTROL 8:8 +#define NVB0B6_VIDEO_COMPOSITOR_SET_CONTROL_PARAMS_CONFIG_STRUCT_SIZE 31:16 +#define NVB0B6_VIDEO_COMPOSITOR_SET_CONFIG_STRUCT_OFFSET (0x00000708) +#define NVB0B6_VIDEO_COMPOSITOR_SET_CONFIG_STRUCT_OFFSET_OFFSET 31:0 +#define NVB0B6_VIDEO_COMPOSITOR_SET_FILTER_STRUCT_OFFSET (0x0000070C) +#define NVB0B6_VIDEO_COMPOSITOR_SET_FILTER_STRUCT_OFFSET_OFFSET 31:0 +#define NVB0B6_VIDEO_COMPOSITOR_SET_PALETTE_OFFSET (0x00000710) +#define NVB0B6_VIDEO_COMPOSITOR_SET_PALETTE_OFFSET_OFFSET 31:0 +#define NVB0B6_VIDEO_COMPOSITOR_SET_HIST_OFFSET (0x00000714) +#define NVB0B6_VIDEO_COMPOSITOR_SET_HIST_OFFSET_OFFSET 31:0 +#define NVB0B6_VIDEO_COMPOSITOR_SET_CONTEXT_ID (0x00000718) +#define NVB0B6_VIDEO_COMPOSITOR_SET_CONTEXT_ID_FCE_UCODE 3:0 +#define NVB0B6_VIDEO_COMPOSITOR_SET_CONTEXT_ID_CONFIG 7:4 +#define NVB0B6_VIDEO_COMPOSITOR_SET_CONTEXT_ID_PALETTE 11:8 +#define NVB0B6_VIDEO_COMPOSITOR_SET_CONTEXT_ID_OUTPUT 15:12 +#define NVB0B6_VIDEO_COMPOSITOR_SET_CONTEXT_ID_HIST 19:16 +#define NVB0B6_VIDEO_COMPOSITOR_SET_FCE_UCODE_SIZE (0x0000071C) +#define NVB0B6_VIDEO_COMPOSITOR_SET_FCE_UCODE_SIZE_FCE_SZ 15:0 +#define NVB0B6_VIDEO_COMPOSITOR_SET_OUTPUT_SURFACE_LUMA_OFFSET (0x00000720) +#define NVB0B6_VIDEO_COMPOSITOR_SET_OUTPUT_SURFACE_LUMA_OFFSET_OFFSET 31:0 +#define NVB0B6_VIDEO_COMPOSITOR_SET_OUTPUT_SURFACE_CHROMA_U_OFFSET (0x00000724) +#define NVB0B6_VIDEO_COMPOSITOR_SET_OUTPUT_SURFACE_CHROMA_U_OFFSET_OFFSET 31:0 +#define NVB0B6_VIDEO_COMPOSITOR_SET_OUTPUT_SURFACE_CHROMA_V_OFFSET (0x00000728) +#define NVB0B6_VIDEO_COMPOSITOR_SET_OUTPUT_SURFACE_CHROMA_V_OFFSET_OFFSET 31:0 +#define NVB0B6_VIDEO_COMPOSITOR_SET_FCE_UCODE_OFFSET (0x0000072C) +#define NVB0B6_VIDEO_COMPOSITOR_SET_FCE_UCODE_OFFSET_OFFSET 31:0 +#define NVB0B6_VIDEO_COMPOSITOR_SET_CRC_STRUCT_OFFSET (0x00000730) +#define NVB0B6_VIDEO_COMPOSITOR_SET_CRC_STRUCT_OFFSET_OFFSET 31:0 +#define NVB0B6_VIDEO_COMPOSITOR_SET_CRC_MODE (0x00000734) +#define NVB0B6_VIDEO_COMPOSITOR_SET_CRC_MODE_INTF_PART_ASEL 3:0 +#define NVB0B6_VIDEO_COMPOSITOR_SET_CRC_MODE_INTF_PART_BSEL 7:4 +#define NVB0B6_VIDEO_COMPOSITOR_SET_CRC_MODE_INTF_PART_CSEL 11:8 +#define NVB0B6_VIDEO_COMPOSITOR_SET_CRC_MODE_INTF_PART_DSEL 15:12 +#define NVB0B6_VIDEO_COMPOSITOR_SET_CRC_MODE_CRC_MODE 16:16 +#define NVB0B6_VIDEO_COMPOSITOR_SET_STATUS_OFFSET (0x00000738) +#define NVB0B6_VIDEO_COMPOSITOR_SET_STATUS_OFFSET_OFFSET 31:0 +#define NVB0B6_VIDEO_COMPOSITOR_SET_SLOT_CONTEXT_ID(b) (0x00000740 + (b)*0x00000004) +#define NVB0B6_VIDEO_COMPOSITOR_SET_SLOT_CONTEXT_ID_CTX_ID_SFC0 3:0 +#define NVB0B6_VIDEO_COMPOSITOR_SET_SLOT_CONTEXT_ID_CTX_ID_SFC1 7:4 +#define NVB0B6_VIDEO_COMPOSITOR_SET_SLOT_CONTEXT_ID_CTX_ID_SFC2 11:8 +#define NVB0B6_VIDEO_COMPOSITOR_SET_SLOT_CONTEXT_ID_CTX_ID_SFC3 15:12 +#define NVB0B6_VIDEO_COMPOSITOR_SET_SLOT_CONTEXT_ID_CTX_ID_SFC4 19:16 +#define NVB0B6_VIDEO_COMPOSITOR_SET_SLOT_CONTEXT_ID_CTX_ID_SFC5 23:20 +#define NVB0B6_VIDEO_COMPOSITOR_SET_SLOT_CONTEXT_ID_CTX_ID_SFC6 27:24 +#define NVB0B6_VIDEO_COMPOSITOR_SET_SLOT_CONTEXT_ID_CTX_ID_SFC7 31:28 +#define NVB0B6_VIDEO_COMPOSITOR_SET_HISTORY_BUFFER_OFFSET(b) (0x00000780 + (b)*0x00000004) +#define NVB0B6_VIDEO_COMPOSITOR_SET_HISTORY_BUFFER_OFFSET_OFFSET 31:0 +#define NVB0B6_VIDEO_COMPOSITOR_SET_COMP_TAG_BUFFER_OFFSET(b) (0x000007C0 + (b)*0x00000004) +#define NVB0B6_VIDEO_COMPOSITOR_SET_COMP_TAG_BUFFER_OFFSET_OFFSET 31:0 +#define NVB0B6_VIDEO_COMPOSITOR_PM_TRIGGER_END (0x00001114) +#define NVB0B6_VIDEO_COMPOSITOR_PM_TRIGGER_END_V 31:0 + +#define NVB0B6_DXVAHD_FRAME_FORMAT_PROGRESSIVE 0 +#define NVB0B6_DXVAHD_FRAME_FORMAT_INTERLACED_TOP_FIELD_FIRST 1 +#define NVB0B6_DXVAHD_FRAME_FORMAT_INTERLACED_BOTTOM_FIELD_FIRST 2 +#define NVB0B6_DXVAHD_FRAME_FORMAT_TOP_FIELD 3 +#define NVB0B6_DXVAHD_FRAME_FORMAT_BOTTOM_FIELD 4 +#define NVB0B6_DXVAHD_FRAME_FORMAT_SUBPIC_PROGRESSIVE 5 +#define NVB0B6_DXVAHD_FRAME_FORMAT_SUBPIC_INTERLACED_TOP_FIELD_FIRST 6 +#define NVB0B6_DXVAHD_FRAME_FORMAT_SUBPIC_INTERLACED_BOTTOM_FIELD_FIRST 7 +#define NVB0B6_DXVAHD_FRAME_FORMAT_SUBPIC_TOP_FIELD 8 +#define NVB0B6_DXVAHD_FRAME_FORMAT_SUBPIC_BOTTOM_FIELD 9 +#define NVB0B6_DXVAHD_FRAME_FORMAT_TOP_FIELD_CHROMA_BOTTOM 10 +#define NVB0B6_DXVAHD_FRAME_FORMAT_BOTTOM_FIELD_CHROMA_TOP 11 +#define NVB0B6_DXVAHD_FRAME_FORMAT_SUBPIC_TOP_FIELD_CHROMA_BOTTOM 12 +#define NVB0B6_DXVAHD_FRAME_FORMAT_SUBPIC_BOTTOM_FIELD_CHROMA_TOP 13 + +#define NVB0B6_T_A8 0 +#define NVB0B6_T_L8 1 +#define NVB0B6_T_A4L4 2 +#define NVB0B6_T_L4A4 3 +#define NVB0B6_T_R8 4 +#define NVB0B6_T_A8L8 5 +#define NVB0B6_T_L8A8 6 +#define NVB0B6_T_R8G8 7 +#define NVB0B6_T_G8R8 8 +#define NVB0B6_T_B5G6R5 9 +#define NVB0B6_T_R5G6B5 10 +#define NVB0B6_T_B6G5R5 11 +#define NVB0B6_T_R5G5B6 12 +#define NVB0B6_T_A1B5G5R5 13 +#define NVB0B6_T_A1R5G5B5 14 +#define NVB0B6_T_B5G5R5A1 15 +#define NVB0B6_T_R5G5B5A1 16 +#define NVB0B6_T_A5B5G5R1 17 +#define NVB0B6_T_A5R1G5B5 18 +#define NVB0B6_T_B5G5R1A5 19 +#define NVB0B6_T_R1G5B5A5 20 +#define NVB0B6_T_X1B5G5R5 21 +#define NVB0B6_T_X1R5G5B5 22 +#define NVB0B6_T_B5G5R5X1 23 +#define NVB0B6_T_R5G5B5X1 24 +#define NVB0B6_T_A4B4G4R4 25 +#define NVB0B6_T_A4R4G4B4 26 +#define NVB0B6_T_B4G4R4A4 27 +#define NVB0B6_T_R4G4B4A4 28 +#define NVB0B6_T_B8_G8_R8 29 +#define NVB0B6_T_R8_G8_B8 30 +#define NVB0B6_T_A8B8G8R8 31 +#define NVB0B6_T_A8R8G8B8 32 +#define NVB0B6_T_B8G8R8A8 33 +#define NVB0B6_T_R8G8B8A8 34 +#define NVB0B6_T_X8B8G8R8 35 +#define NVB0B6_T_X8R8G8B8 36 +#define NVB0B6_T_B8G8R8X8 37 +#define NVB0B6_T_R8G8B8X8 38 +#define NVB0B6_T_A2B10G10R10 39 +#define NVB0B6_T_A2R10G10B10 40 +#define NVB0B6_T_B10G10R10A2 41 +#define NVB0B6_T_R10G10B10A2 42 +#define NVB0B6_T_A4P4 43 +#define NVB0B6_T_P4A4 44 +#define NVB0B6_T_P8A8 45 +#define NVB0B6_T_A8P8 46 +#define NVB0B6_T_P8 47 +#define NVB0B6_T_P1 48 +#define NVB0B6_T_U8V8 49 +#define NVB0B6_T_V8U8 50 +#define NVB0B6_T_A8Y8U8V8 51 +#define NVB0B6_T_V8U8Y8A8 52 +#define NVB0B6_T_Y8_U8_V8 53 +#define NVB0B6_T_Y8_V8_U8 54 +#define NVB0B6_T_U8_V8_Y8 55 +#define NVB0B6_T_V8_U8_Y8 56 +#define NVB0B6_T_Y8_U8__Y8_V8 57 +#define NVB0B6_T_Y8_V8__Y8_U8 58 +#define NVB0B6_T_U8_Y8__V8_Y8 59 +#define NVB0B6_T_V8_Y8__U8_Y8 60 +#define NVB0B6_T_Y8___U8V8_N444 61 +#define NVB0B6_T_Y8___V8U8_N444 62 +#define NVB0B6_T_Y8___U8V8_N422 63 +#define NVB0B6_T_Y8___V8U8_N422 64 +#define NVB0B6_T_Y8___U8V8_N422R 65 +#define NVB0B6_T_Y8___V8U8_N422R 66 +#define NVB0B6_T_Y8___U8V8_N420 67 +#define NVB0B6_T_Y8___V8U8_N420 68 +#define NVB0B6_T_Y8___U8___V8_N444 69 +#define NVB0B6_T_Y8___U8___V8_N422 70 +#define NVB0B6_T_Y8___U8___V8_N422R 71 +#define NVB0B6_T_Y8___U8___V8_N420 72 +#define NVB0B6_T_U8 73 +#define NVB0B6_T_V8 74 + +#define NVB0B6_DXVAHD_ALPHA_FILL_MODE_OPAQUE 0 +#define NVB0B6_DXVAHD_ALPHA_FILL_MODE_BACKGROUND 1 +#define NVB0B6_DXVAHD_ALPHA_FILL_MODE_DESTINATION 2 +#define NVB0B6_DXVAHD_ALPHA_FILL_MODE_SOURCE_STREAM 3 +#define NVB0B6_DXVAHD_ALPHA_FILL_MODE_COMPOSITED 4 +#define NVB0B6_DXVAHD_ALPHA_FILL_MODE_SOURCE_ALPHA 5 + +#define NVB0B6_BLK_KIND_PITCH 0 +#define NVB0B6_BLK_KIND_GENERIC_16Bx2 1 +#define NVB0B6_BLK_KIND_BL_NAIVE 2 +#define NVB0B6_BLK_KIND_BL_KEPLER_XBAR_RAW 3 +#define NVB0B6_BLK_KIND_VP2_TILED 15 + +#define NVB0B6_FILTER_LENGTH_1TAP 0 +#define NVB0B6_FILTER_LENGTH_2TAP 1 +#define NVB0B6_FILTER_LENGTH_5TAP 2 +#define NVB0B6_FILTER_LENGTH_10TAP 3 + +#define NVB0B6_FILTER_TYPE_NORMAL 0 +#define NVB0B6_FILTER_TYPE_NOISE 1 +#define NVB0B6_FILTER_TYPE_DETAIL 2 + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif /* AVUTIL_CLB0B6_H */ diff --git a/libavutil/clc5b0.h b/libavutil/clc5b0.h new file mode 100644 index 0000000000..f7957bf46a --- /dev/null +++ b/libavutil/clc5b0.h @@ -0,0 +1,436 @@ +/******************************************************************************* + Copyright (c) 1993-2020, NVIDIA CORPORATION. All rights reserved. + + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + +*******************************************************************************/ + +#ifndef AVUTIL_CLC5B0_H +#define AVUTIL_CLC5B0_H + +#ifdef __cplusplus +extern "C" { +#endif + +#define NVC5B0_VIDEO_DECODER (0x0000C5B0) + +#define NVC5B0_NOP (0x00000100) +#define NVC5B0_NOP_PARAMETER 31:0 +#define NVC5B0_SET_APPLICATION_ID (0x00000200) +#define NVC5B0_SET_APPLICATION_ID_ID 31:0 +#define NVC5B0_SET_APPLICATION_ID_ID_MPEG12 (0x00000001) +#define NVC5B0_SET_APPLICATION_ID_ID_VC1 (0x00000002) +#define NVC5B0_SET_APPLICATION_ID_ID_H264 (0x00000003) +#define NVC5B0_SET_APPLICATION_ID_ID_MPEG4 (0x00000004) +#define NVC5B0_SET_APPLICATION_ID_ID_VP8 (0x00000005) +#define NVC5B0_SET_APPLICATION_ID_ID_HEVC (0x00000007) +#define NVC5B0_SET_APPLICATION_ID_ID_VP9 (0x00000009) +#define NVC5B0_SET_APPLICATION_ID_ID_HEVC_PARSER (0x0000000C) +#define NVC5B0_SET_WATCHDOG_TIMER (0x00000204) +#define NVC5B0_SET_WATCHDOG_TIMER_TIMER 31:0 +#define NVC5B0_SEMAPHORE_A (0x00000240) +#define NVC5B0_SEMAPHORE_A_UPPER 7:0 +#define NVC5B0_SEMAPHORE_B (0x00000244) +#define NVC5B0_SEMAPHORE_B_LOWER 31:0 +#define NVC5B0_SEMAPHORE_C (0x00000248) +#define NVC5B0_SEMAPHORE_C_PAYLOAD 31:0 +#define NVC5B0_CTX_SAVE_AREA (0x0000024C) +#define NVC5B0_CTX_SAVE_AREA_OFFSET 31:0 +#define NVC5B0_CTX_SWITCH (0x00000250) +#define NVC5B0_CTX_SWITCH_OP 1:0 +#define NVC5B0_CTX_SWITCH_OP_CTX_UPDATE (0x00000000) +#define NVC5B0_CTX_SWITCH_OP_CTX_SAVE (0x00000001) +#define NVC5B0_CTX_SWITCH_OP_CTX_RESTORE (0x00000002) +#define NVC5B0_CTX_SWITCH_OP_CTX_FORCERESTORE (0x00000003) +#define NVC5B0_CTX_SWITCH_CTXID_VALID 2:2 +#define NVC5B0_CTX_SWITCH_CTXID_VALID_FALSE (0x00000000) +#define NVC5B0_CTX_SWITCH_CTXID_VALID_TRUE (0x00000001) +#define NVC5B0_CTX_SWITCH_RESERVED0 7:3 +#define NVC5B0_CTX_SWITCH_CTX_ID 23:8 +#define NVC5B0_CTX_SWITCH_RESERVED1 31:24 +#define NVC5B0_EXECUTE (0x00000300) +#define NVC5B0_EXECUTE_NOTIFY 0:0 +#define NVC5B0_EXECUTE_NOTIFY_DISABLE (0x00000000) +#define NVC5B0_EXECUTE_NOTIFY_ENABLE (0x00000001) +#define NVC5B0_EXECUTE_NOTIFY_ON 1:1 +#define NVC5B0_EXECUTE_NOTIFY_ON_END (0x00000000) +#define NVC5B0_EXECUTE_NOTIFY_ON_BEGIN (0x00000001) +#define NVC5B0_EXECUTE_AWAKEN 8:8 +#define NVC5B0_EXECUTE_AWAKEN_DISABLE (0x00000000) +#define NVC5B0_EXECUTE_AWAKEN_ENABLE (0x00000001) +#define NVC5B0_SEMAPHORE_D (0x00000304) +#define NVC5B0_SEMAPHORE_D_STRUCTURE_SIZE 0:0 +#define NVC5B0_SEMAPHORE_D_STRUCTURE_SIZE_ONE (0x00000000) +#define NVC5B0_SEMAPHORE_D_STRUCTURE_SIZE_FOUR (0x00000001) +#define NVC5B0_SEMAPHORE_D_AWAKEN_ENABLE 8:8 +#define NVC5B0_SEMAPHORE_D_AWAKEN_ENABLE_FALSE (0x00000000) +#define NVC5B0_SEMAPHORE_D_AWAKEN_ENABLE_TRUE (0x00000001) +#define NVC5B0_SEMAPHORE_D_OPERATION 17:16 +#define NVC5B0_SEMAPHORE_D_OPERATION_RELEASE (0x00000000) +#define NVC5B0_SEMAPHORE_D_OPERATION_RESERVED0 (0x00000001) +#define NVC5B0_SEMAPHORE_D_OPERATION_RESERVED1 (0x00000002) +#define NVC5B0_SEMAPHORE_D_OPERATION_TRAP (0x00000003) +#define NVC5B0_SEMAPHORE_D_FLUSH_DISABLE 21:21 +#define NVC5B0_SEMAPHORE_D_FLUSH_DISABLE_FALSE (0x00000000) +#define NVC5B0_SEMAPHORE_D_FLUSH_DISABLE_TRUE (0x00000001) +#define NVC5B0_SET_CONTROL_PARAMS (0x00000400) +#define NVC5B0_SET_CONTROL_PARAMS_CODEC_TYPE 3:0 +#define NVC5B0_SET_CONTROL_PARAMS_CODEC_TYPE_MPEG1 (0x00000000) +#define NVC5B0_SET_CONTROL_PARAMS_CODEC_TYPE_MPEG2 (0x00000001) +#define NVC5B0_SET_CONTROL_PARAMS_CODEC_TYPE_VC1 (0x00000002) +#define NVC5B0_SET_CONTROL_PARAMS_CODEC_TYPE_H264 (0x00000003) +#define NVC5B0_SET_CONTROL_PARAMS_CODEC_TYPE_MPEG4 (0x00000004) +#define NVC5B0_SET_CONTROL_PARAMS_CODEC_TYPE_DIVX3 (0x00000004) +#define NVC5B0_SET_CONTROL_PARAMS_CODEC_TYPE_VP8 (0x00000005) +#define NVC5B0_SET_CONTROL_PARAMS_CODEC_TYPE_HEVC (0x00000007) +#define NVC5B0_SET_CONTROL_PARAMS_CODEC_TYPE_VP9 (0x00000009) +#define NVC5B0_SET_CONTROL_PARAMS_GPTIMER_ON 4:4 +#define NVC5B0_SET_CONTROL_PARAMS_RET_ERROR 5:5 +#define NVC5B0_SET_CONTROL_PARAMS_ERR_CONCEAL_ON 6:6 +#define NVC5B0_SET_CONTROL_PARAMS_ERROR_FRM_IDX 12:7 +#define NVC5B0_SET_CONTROL_PARAMS_MBTIMER_ON 13:13 +#define NVC5B0_SET_CONTROL_PARAMS_EC_INTRA_FRAME_USING_PSLC 14:14 +#define NVC5B0_SET_CONTROL_PARAMS_ALL_INTRA_FRAME 17:17 +#define NVC5B0_SET_CONTROL_PARAMS_RESERVED 31:18 +#define NVC5B0_SET_DRV_PIC_SETUP_OFFSET (0x00000404) +#define NVC5B0_SET_DRV_PIC_SETUP_OFFSET_OFFSET 31:0 +#define NVC5B0_SET_IN_BUF_BASE_OFFSET (0x00000408) +#define NVC5B0_SET_IN_BUF_BASE_OFFSET_OFFSET 31:0 +#define NVC5B0_SET_PICTURE_INDEX (0x0000040C) +#define NVC5B0_SET_PICTURE_INDEX_INDEX 31:0 +#define NVC5B0_SET_SLICE_OFFSETS_BUF_OFFSET (0x00000410) +#define NVC5B0_SET_SLICE_OFFSETS_BUF_OFFSET_OFFSET 31:0 +#define NVC5B0_SET_COLOC_DATA_OFFSET (0x00000414) +#define NVC5B0_SET_COLOC_DATA_OFFSET_OFFSET 31:0 +#define NVC5B0_SET_HISTORY_OFFSET (0x00000418) +#define NVC5B0_SET_HISTORY_OFFSET_OFFSET 31:0 +#define NVC5B0_SET_DISPLAY_BUF_SIZE (0x0000041C) +#define NVC5B0_SET_DISPLAY_BUF_SIZE_SIZE 31:0 +#define NVC5B0_SET_HISTOGRAM_OFFSET (0x00000420) +#define NVC5B0_SET_HISTOGRAM_OFFSET_OFFSET 31:0 +#define NVC5B0_SET_NVDEC_STATUS_OFFSET (0x00000424) +#define NVC5B0_SET_NVDEC_STATUS_OFFSET_OFFSET 31:0 +#define NVC5B0_SET_DISPLAY_BUF_LUMA_OFFSET (0x00000428) +#define NVC5B0_SET_DISPLAY_BUF_LUMA_OFFSET_OFFSET 31:0 +#define NVC5B0_SET_DISPLAY_BUF_CHROMA_OFFSET (0x0000042C) +#define NVC5B0_SET_DISPLAY_BUF_CHROMA_OFFSET_OFFSET 31:0 +#define NVC5B0_SET_PICTURE_LUMA_OFFSET0 (0x00000430) +#define NVC5B0_SET_PICTURE_LUMA_OFFSET0_OFFSET 31:0 +#define NVC5B0_SET_PICTURE_LUMA_OFFSET1 (0x00000434) +#define NVC5B0_SET_PICTURE_LUMA_OFFSET1_OFFSET 31:0 +#define NVC5B0_SET_PICTURE_LUMA_OFFSET2 (0x00000438) +#define NVC5B0_SET_PICTURE_LUMA_OFFSET2_OFFSET 31:0 +#define NVC5B0_SET_PICTURE_LUMA_OFFSET3 (0x0000043C) +#define NVC5B0_SET_PICTURE_LUMA_OFFSET3_OFFSET 31:0 +#define NVC5B0_SET_PICTURE_LUMA_OFFSET4 (0x00000440) +#define NVC5B0_SET_PICTURE_LUMA_OFFSET4_OFFSET 31:0 +#define NVC5B0_SET_PICTURE_LUMA_OFFSET5 (0x00000444) +#define NVC5B0_SET_PICTURE_LUMA_OFFSET5_OFFSET 31:0 +#define NVC5B0_SET_PICTURE_LUMA_OFFSET6 (0x00000448) +#define NVC5B0_SET_PICTURE_LUMA_OFFSET6_OFFSET 31:0 +#define NVC5B0_SET_PICTURE_LUMA_OFFSET7 (0x0000044C) +#define NVC5B0_SET_PICTURE_LUMA_OFFSET7_OFFSET 31:0 +#define NVC5B0_SET_PICTURE_LUMA_OFFSET8 (0x00000450) +#define NVC5B0_SET_PICTURE_LUMA_OFFSET8_OFFSET 31:0 +#define NVC5B0_SET_PICTURE_LUMA_OFFSET9 (0x00000454) +#define NVC5B0_SET_PICTURE_LUMA_OFFSET9_OFFSET 31:0 +#define NVC5B0_SET_PICTURE_LUMA_OFFSET10 (0x00000458) +#define NVC5B0_SET_PICTURE_LUMA_OFFSET10_OFFSET 31:0 +#define NVC5B0_SET_PICTURE_LUMA_OFFSET11 (0x0000045C) +#define NVC5B0_SET_PICTURE_LUMA_OFFSET11_OFFSET 31:0 +#define NVC5B0_SET_PICTURE_LUMA_OFFSET12 (0x00000460) +#define NVC5B0_SET_PICTURE_LUMA_OFFSET12_OFFSET 31:0 +#define NVC5B0_SET_PICTURE_LUMA_OFFSET13 (0x00000464) +#define NVC5B0_SET_PICTURE_LUMA_OFFSET13_OFFSET 31:0 +#define NVC5B0_SET_PICTURE_LUMA_OFFSET14 (0x00000468) +#define NVC5B0_SET_PICTURE_LUMA_OFFSET14_OFFSET 31:0 +#define NVC5B0_SET_PICTURE_LUMA_OFFSET15 (0x0000046C) +#define NVC5B0_SET_PICTURE_LUMA_OFFSET15_OFFSET 31:0 +#define NVC5B0_SET_PICTURE_LUMA_OFFSET16 (0x00000470) +#define NVC5B0_SET_PICTURE_LUMA_OFFSET16_OFFSET 31:0 +#define NVC5B0_SET_PICTURE_CHROMA_OFFSET0 (0x00000474) +#define NVC5B0_SET_PICTURE_CHROMA_OFFSET0_OFFSET 31:0 +#define NVC5B0_SET_PICTURE_CHROMA_OFFSET1 (0x00000478) +#define NVC5B0_SET_PICTURE_CHROMA_OFFSET1_OFFSET 31:0 +#define NVC5B0_SET_PICTURE_CHROMA_OFFSET2 (0x0000047C) +#define NVC5B0_SET_PICTURE_CHROMA_OFFSET2_OFFSET 31:0 +#define NVC5B0_SET_PICTURE_CHROMA_OFFSET3 (0x00000480) +#define NVC5B0_SET_PICTURE_CHROMA_OFFSET3_OFFSET 31:0 +#define NVC5B0_SET_PICTURE_CHROMA_OFFSET4 (0x00000484) +#define NVC5B0_SET_PICTURE_CHROMA_OFFSET4_OFFSET 31:0 +#define NVC5B0_SET_PICTURE_CHROMA_OFFSET5 (0x00000488) +#define NVC5B0_SET_PICTURE_CHROMA_OFFSET5_OFFSET 31:0 +#define NVC5B0_SET_PICTURE_CHROMA_OFFSET6 (0x0000048C) +#define NVC5B0_SET_PICTURE_CHROMA_OFFSET6_OFFSET 31:0 +#define NVC5B0_SET_PICTURE_CHROMA_OFFSET7 (0x00000490) +#define NVC5B0_SET_PICTURE_CHROMA_OFFSET7_OFFSET 31:0 +#define NVC5B0_SET_PICTURE_CHROMA_OFFSET8 (0x00000494) +#define NVC5B0_SET_PICTURE_CHROMA_OFFSET8_OFFSET 31:0 +#define NVC5B0_SET_PICTURE_CHROMA_OFFSET9 (0x00000498) +#define NVC5B0_SET_PICTURE_CHROMA_OFFSET9_OFFSET 31:0 +#define NVC5B0_SET_PICTURE_CHROMA_OFFSET10 (0x0000049C) +#define NVC5B0_SET_PICTURE_CHROMA_OFFSET10_OFFSET 31:0 +#define NVC5B0_SET_PICTURE_CHROMA_OFFSET11 (0x000004A0) +#define NVC5B0_SET_PICTURE_CHROMA_OFFSET11_OFFSET 31:0 +#define NVC5B0_SET_PICTURE_CHROMA_OFFSET12 (0x000004A4) +#define NVC5B0_SET_PICTURE_CHROMA_OFFSET12_OFFSET 31:0 +#define NVC5B0_SET_PICTURE_CHROMA_OFFSET13 (0x000004A8) +#define NVC5B0_SET_PICTURE_CHROMA_OFFSET13_OFFSET 31:0 +#define NVC5B0_SET_PICTURE_CHROMA_OFFSET14 (0x000004AC) +#define NVC5B0_SET_PICTURE_CHROMA_OFFSET14_OFFSET 31:0 +#define NVC5B0_SET_PICTURE_CHROMA_OFFSET15 (0x000004B0) +#define NVC5B0_SET_PICTURE_CHROMA_OFFSET15_OFFSET 31:0 +#define NVC5B0_SET_PICTURE_CHROMA_OFFSET16 (0x000004B4) +#define NVC5B0_SET_PICTURE_CHROMA_OFFSET16_OFFSET 31:0 +#define NVC5B0_SET_PIC_SCRATCH_BUF_OFFSET (0x000004B8) +#define NVC5B0_SET_PIC_SCRATCH_BUF_OFFSET_OFFSET 31:0 +#define NVC5B0_SET_EXTERNAL_MVBUFFER_OFFSET (0x000004BC) +#define NVC5B0_SET_EXTERNAL_MVBUFFER_OFFSET_OFFSET 31:0 +#define NVC5B0_H264_SET_MBHIST_BUF_OFFSET (0x00000500) +#define NVC5B0_H264_SET_MBHIST_BUF_OFFSET_OFFSET 31:0 +#define NVC5B0_VP8_SET_PROB_DATA_OFFSET (0x00000540) +#define NVC5B0_VP8_SET_PROB_DATA_OFFSET_OFFSET 31:0 +#define NVC5B0_VP8_SET_HEADER_PARTITION_BUF_BASE_OFFSET (0x00000544) +#define NVC5B0_VP8_SET_HEADER_PARTITION_BUF_BASE_OFFSET_OFFSET 31:0 +#define NVC5B0_HEVC_SET_SCALING_LIST_OFFSET (0x00000580) +#define NVC5B0_HEVC_SET_SCALING_LIST_OFFSET_OFFSET 31:0 +#define NVC5B0_HEVC_SET_TILE_SIZES_OFFSET (0x00000584) +#define NVC5B0_HEVC_SET_TILE_SIZES_OFFSET_OFFSET 31:0 +#define NVC5B0_HEVC_SET_FILTER_BUFFER_OFFSET (0x00000588) +#define NVC5B0_HEVC_SET_FILTER_BUFFER_OFFSET_OFFSET 31:0 +#define NVC5B0_HEVC_SET_SAO_BUFFER_OFFSET (0x0000058C) +#define NVC5B0_HEVC_SET_SAO_BUFFER_OFFSET_OFFSET 31:0 +#define NVC5B0_HEVC_SET_SLICE_INFO_BUFFER_OFFSET (0x00000590) +#define NVC5B0_HEVC_SET_SLICE_INFO_BUFFER_OFFSET_OFFSET 31:0 +#define NVC5B0_HEVC_SET_SLICE_GROUP_INDEX (0x00000594) +#define NVC5B0_HEVC_SET_SLICE_GROUP_INDEX_OFFSET 31:0 +#define NVC5B0_VP9_SET_PROB_TAB_BUF_OFFSET (0x000005C0) +#define NVC5B0_VP9_SET_PROB_TAB_BUF_OFFSET_OFFSET 31:0 +#define NVC5B0_VP9_SET_CTX_COUNTER_BUF_OFFSET (0x000005C4) +#define NVC5B0_VP9_SET_CTX_COUNTER_BUF_OFFSET_OFFSET 31:0 +#define NVC5B0_VP9_SET_SEGMENT_READ_BUF_OFFSET (0x000005C8) +#define NVC5B0_VP9_SET_SEGMENT_READ_BUF_OFFSET_OFFSET 31:0 +#define NVC5B0_VP9_SET_SEGMENT_WRITE_BUF_OFFSET (0x000005CC) +#define NVC5B0_VP9_SET_SEGMENT_WRITE_BUF_OFFSET_OFFSET 31:0 +#define NVC5B0_VP9_SET_TILE_SIZE_BUF_OFFSET (0x000005D0) +#define NVC5B0_VP9_SET_TILE_SIZE_BUF_OFFSET_OFFSET 31:0 +#define NVC5B0_VP9_SET_COL_MVWRITE_BUF_OFFSET (0x000005D4) +#define NVC5B0_VP9_SET_COL_MVWRITE_BUF_OFFSET_OFFSET 31:0 +#define NVC5B0_VP9_SET_COL_MVREAD_BUF_OFFSET (0x000005D8) +#define NVC5B0_VP9_SET_COL_MVREAD_BUF_OFFSET_OFFSET 31:0 +#define NVC5B0_VP9_SET_FILTER_BUFFER_OFFSET (0x000005DC) +#define NVC5B0_VP9_SET_FILTER_BUFFER_OFFSET_OFFSET 31:0 + +#define NVC5B0_ERROR_NONE (0x00000000) +#define NVC5B0_OS_ERROR_EXECUTE_INSUFFICIENT_DATA (0x00000001) +#define NVC5B0_OS_ERROR_SEMAPHORE_INSUFFICIENT_DATA (0x00000002) +#define NVC5B0_OS_ERROR_INVALID_METHOD (0x00000003) +#define NVC5B0_OS_ERROR_INVALID_DMA_PAGE (0x00000004) +#define NVC5B0_OS_ERROR_UNHANDLED_INTERRUPT (0x00000005) +#define NVC5B0_OS_ERROR_EXCEPTION (0x00000006) +#define NVC5B0_OS_ERROR_INVALID_CTXSW_REQUEST (0x00000007) +#define NVC5B0_OS_ERROR_APPLICATION (0x00000008) +#define NVC5B0_OS_ERROR_SW_BREAKPT (0x00000009) +#define NVC5B0_OS_INTERRUPT_EXECUTE_AWAKEN (0x00000100) +#define NVC5B0_OS_INTERRUPT_BACKEND_SEMAPHORE_AWAKEN (0x00000200) +#define NVC5B0_OS_INTERRUPT_CTX_ERROR_FBIF (0x00000300) +#define NVC5B0_OS_INTERRUPT_LIMIT_VIOLATION (0x00000400) +#define NVC5B0_OS_INTERRUPT_LIMIT_AND_FBIF_CTX_ERROR (0x00000500) +#define NVC5B0_OS_INTERRUPT_HALT_ENGINE (0x00000600) +#define NVC5B0_OS_INTERRUPT_TRAP_NONSTALL (0x00000700) +#define NVC5B0_H264_VLD_ERR_SEQ_DATA_INCONSISTENT (0x00004001) +#define NVC5B0_H264_VLD_ERR_PIC_DATA_INCONSISTENT (0x00004002) +#define NVC5B0_H264_VLD_ERR_SLC_DATA_BUF_ADDR_OUT_OF_BOUNDS (0x00004100) +#define NVC5B0_H264_VLD_ERR_BITSTREAM_ERROR (0x00004101) +#define NVC5B0_H264_VLD_ERR_CTX_DMA_ID_CTRL_IN_INVALID (0x000041F8) +#define NVC5B0_H264_VLD_ERR_SLC_HDR_OUT_SIZE_NOT_MULT256 (0x00004200) +#define NVC5B0_H264_VLD_ERR_SLC_DATA_OUT_SIZE_NOT_MULT256 (0x00004201) +#define NVC5B0_H264_VLD_ERR_CTX_DMA_ID_FLOW_CTRL_INVALID (0x00004203) +#define NVC5B0_H264_VLD_ERR_CTX_DMA_ID_SLC_HDR_OUT_INVALID (0x00004204) +#define NVC5B0_H264_VLD_ERR_SLC_HDR_OUT_BUF_TOO_SMALL (0x00004205) +#define NVC5B0_H264_VLD_ERR_SLC_HDR_OUT_BUF_ALREADY_VALID (0x00004206) +#define NVC5B0_H264_VLD_ERR_SLC_DATA_OUT_BUF_TOO_SMALL (0x00004207) +#define NVC5B0_H264_VLD_ERR_DATA_BUF_CNT_TOO_SMALL (0x00004208) +#define NVC5B0_H264_VLD_ERR_BITSTREAM_EMPTY (0x00004209) +#define NVC5B0_H264_VLD_ERR_FRAME_WIDTH_TOO_LARGE (0x0000420A) +#define NVC5B0_H264_VLD_ERR_FRAME_HEIGHT_TOO_LARGE (0x0000420B) +#define NVC5B0_H264_VLD_ERR_HIST_BUF_TOO_SMALL (0x00004300) +#define NVC5B0_VC1_VLD_ERR_PIC_DATA_BUF_ADDR_OUT_OF_BOUND (0x00005100) +#define NVC5B0_VC1_VLD_ERR_BITSTREAM_ERROR (0x00005101) +#define NVC5B0_VC1_VLD_ERR_PIC_HDR_OUT_SIZE_NOT_MULT256 (0x00005200) +#define NVC5B0_VC1_VLD_ERR_PIC_DATA_OUT_SIZE_NOT_MULT256 (0x00005201) +#define NVC5B0_VC1_VLD_ERR_CTX_DMA_ID_CTRL_IN_INVALID (0x00005202) +#define NVC5B0_VC1_VLD_ERR_CTX_DMA_ID_FLOW_CTRL_INVALID (0x00005203) +#define NVC5B0_VC1_VLD_ERR_CTX_DMA_ID_PIC_HDR_OUT_INVALID (0x00005204) +#define NVC5B0_VC1_VLD_ERR_SLC_HDR_OUT_BUF_TOO_SMALL (0x00005205) +#define NVC5B0_VC1_VLD_ERR_PIC_HDR_OUT_BUF_ALREADY_VALID (0x00005206) +#define NVC5B0_VC1_VLD_ERR_PIC_DATA_OUT_BUF_TOO_SMALL (0x00005207) +#define NVC5B0_VC1_VLD_ERR_DATA_INFO_IN_BUF_TOO_SMALL (0x00005208) +#define NVC5B0_VC1_VLD_ERR_BITSTREAM_EMPTY (0x00005209) +#define NVC5B0_VC1_VLD_ERR_FRAME_WIDTH_TOO_LARGE (0x0000520A) +#define NVC5B0_VC1_VLD_ERR_FRAME_HEIGHT_TOO_LARGE (0x0000520B) +#define NVC5B0_VC1_VLD_ERR_PIC_DATA_OUT_BUF_FULL_TIME_OUT (0x00005300) +#define NVC5B0_MPEG12_VLD_ERR_SLC_DATA_BUF_ADDR_OUT_OF_BOUNDS (0x00006100) +#define NVC5B0_MPEG12_VLD_ERR_BITSTREAM_ERROR (0x00006101) +#define NVC5B0_MPEG12_VLD_ERR_SLC_DATA_OUT_SIZE_NOT_MULT256 (0x00006200) +#define NVC5B0_MPEG12_VLD_ERR_CTX_DMA_ID_CTRL_IN_INVALID (0x00006201) +#define NVC5B0_MPEG12_VLD_ERR_CTX_DMA_ID_FLOW_CTRL_INVALID (0x00006202) +#define NVC5B0_MPEG12_VLD_ERR_SLC_DATA_OUT_BUF_TOO_SMALL (0x00006203) +#define NVC5B0_MPEG12_VLD_ERR_DATA_INFO_IN_BUF_TOO_SMALL (0x00006204) +#define NVC5B0_MPEG12_VLD_ERR_BITSTREAM_EMPTY (0x00006205) +#define NVC5B0_MPEG12_VLD_ERR_INVALID_PIC_STRUCTURE (0x00006206) +#define NVC5B0_MPEG12_VLD_ERR_INVALID_PIC_CODING_TYPE (0x00006207) +#define NVC5B0_MPEG12_VLD_ERR_FRAME_WIDTH_TOO_LARGE (0x00006208) +#define NVC5B0_MPEG12_VLD_ERR_FRAME_HEIGHT_TOO_LARGE (0x00006209) +#define NVC5B0_MPEG12_VLD_ERR_SLC_DATA_OUT_BUF_FULL_TIME_OUT (0x00006300) +#define NVC5B0_CMN_VLD_ERR_PDEC_RETURNED_ERROR (0x00007101) +#define NVC5B0_CMN_VLD_ERR_EDOB_FLUSH_TIME_OUT (0x00007102) +#define NVC5B0_CMN_VLD_ERR_EDOB_REWIND_TIME_OUT (0x00007103) +#define NVC5B0_CMN_VLD_ERR_VLD_WD_TIME_OUT (0x00007104) +#define NVC5B0_CMN_VLD_ERR_NUM_SLICES_ZERO (0x00007105) +#define NVC5B0_MPEG4_VLD_ERR_PIC_DATA_BUF_ADDR_OUT_OF_BOUND (0x00008100) +#define NVC5B0_MPEG4_VLD_ERR_BITSTREAM_ERROR (0x00008101) +#define NVC5B0_MPEG4_VLD_ERR_PIC_HDR_OUT_SIZE_NOT_MULT256 (0x00008200) +#define NVC5B0_MPEG4_VLD_ERR_PIC_DATA_OUT_SIZE_NOT_MULT256 (0x00008201) +#define NVC5B0_MPEG4_VLD_ERR_CTX_DMA_ID_CTRL_IN_INVALID (0x00008202) +#define NVC5B0_MPEG4_VLD_ERR_CTX_DMA_ID_FLOW_CTRL_INVALID (0x00008203) +#define NVC5B0_MPEG4_VLD_ERR_CTX_DMA_ID_PIC_HDR_OUT_INVALID (0x00008204) +#define NVC5B0_MPEG4_VLD_ERR_SLC_HDR_OUT_BUF_TOO_SMALL (0x00008205) +#define NVC5B0_MPEG4_VLD_ERR_PIC_HDR_OUT_BUF_ALREADY_VALID (0x00008206) +#define NVC5B0_MPEG4_VLD_ERR_PIC_DATA_OUT_BUF_TOO_SMALL (0x00008207) +#define NVC5B0_MPEG4_VLD_ERR_DATA_INFO_IN_BUF_TOO_SMALL (0x00008208) +#define NVC5B0_MPEG4_VLD_ERR_BITSTREAM_EMPTY (0x00008209) +#define NVC5B0_MPEG4_VLD_ERR_FRAME_WIDTH_TOO_LARGE (0x0000820A) +#define NVC5B0_MPEG4_VLD_ERR_FRAME_HEIGHT_TOO_LARGE (0x0000820B) +#define NVC5B0_MPEG4_VLD_ERR_PIC_DATA_OUT_BUF_FULL_TIME_OUT (0x00051E01) +#define NVC5B0_DEC_ERROR_MPEG12_APPTIMER_EXPIRED (0xDEC10001) +#define NVC5B0_DEC_ERROR_MPEG12_MVTIMER_EXPIRED (0xDEC10002) +#define NVC5B0_DEC_ERROR_MPEG12_INVALID_TOKEN (0xDEC10003) +#define NVC5B0_DEC_ERROR_MPEG12_SLICEDATA_MISSING (0xDEC10004) +#define NVC5B0_DEC_ERROR_MPEG12_HWERR_INTERRUPT (0xDEC10005) +#define NVC5B0_DEC_ERROR_MPEG12_DETECTED_VLD_FAILURE (0xDEC10006) +#define NVC5B0_DEC_ERROR_MPEG12_PICTURE_INIT (0xDEC10100) +#define NVC5B0_DEC_ERROR_MPEG12_STATEMACHINE_FAILURE (0xDEC10101) +#define NVC5B0_DEC_ERROR_MPEG12_INVALID_CTXID_PIC (0xDEC10901) +#define NVC5B0_DEC_ERROR_MPEG12_INVALID_CTXID_UCODE (0xDEC10902) +#define NVC5B0_DEC_ERROR_MPEG12_INVALID_CTXID_FC (0xDEC10903) +#define NVC5B0_DEC_ERROR_MPEG12_INVALID_CTXID_SLH (0xDEC10904) +#define NVC5B0_DEC_ERROR_MPEG12_INVALID_UCODE_SIZE (0xDEC10905) +#define NVC5B0_DEC_ERROR_MPEG12_INVALID_SLICE_COUNT (0xDEC10906) +#define NVC5B0_DEC_ERROR_VC1_APPTIMER_EXPIRED (0xDEC20001) +#define NVC5B0_DEC_ERROR_VC1_MVTIMER_EXPIRED (0xDEC20002) +#define NVC5B0_DEC_ERROR_VC1_INVALID_TOKEN (0xDEC20003) +#define NVC5B0_DEC_ERROR_VC1_SLICEDATA_MISSING (0xDEC20004) +#define NVC5B0_DEC_ERROR_VC1_HWERR_INTERRUPT (0xDEC20005) +#define NVC5B0_DEC_ERROR_VC1_DETECTED_VLD_FAILURE (0xDEC20006) +#define NVC5B0_DEC_ERROR_VC1_TIMEOUT_POLLING_FOR_DATA (0xDEC20007) +#define NVC5B0_DEC_ERROR_VC1_PDEC_PIC_END_UNALIGNED (0xDEC20008) +#define NVC5B0_DEC_ERROR_VC1_WDTIMER_EXPIRED (0xDEC20009) +#define NVC5B0_DEC_ERROR_VC1_ERRINTSTART (0xDEC20010) +#define NVC5B0_DEC_ERROR_VC1_IQT_ERRINT (0xDEC20011) +#define NVC5B0_DEC_ERROR_VC1_MC_ERRINT (0xDEC20012) +#define NVC5B0_DEC_ERROR_VC1_MC_IQT_ERRINT (0xDEC20013) +#define NVC5B0_DEC_ERROR_VC1_REC_ERRINT (0xDEC20014) +#define NVC5B0_DEC_ERROR_VC1_REC_IQT_ERRINT (0xDEC20015) +#define NVC5B0_DEC_ERROR_VC1_REC_MC_ERRINT (0xDEC20016) +#define NVC5B0_DEC_ERROR_VC1_REC_MC_IQT_ERRINT (0xDEC20017) +#define NVC5B0_DEC_ERROR_VC1_DBF_ERRINT (0xDEC20018) +#define NVC5B0_DEC_ERROR_VC1_DBF_IQT_ERRINT (0xDEC20019) +#define NVC5B0_DEC_ERROR_VC1_DBF_MC_ERRINT (0xDEC2001A) +#define NVC5B0_DEC_ERROR_VC1_DBF_MC_IQT_ERRINT (0xDEC2001B) +#define NVC5B0_DEC_ERROR_VC1_DBF_REC_ERRINT (0xDEC2001C) +#define NVC5B0_DEC_ERROR_VC1_DBF_REC_IQT_ERRINT (0xDEC2001D) +#define NVC5B0_DEC_ERROR_VC1_DBF_REC_MC_ERRINT (0xDEC2001E) +#define NVC5B0_DEC_ERROR_VC1_DBF_REC_MC_IQT_ERRINT (0xDEC2001F) +#define NVC5B0_DEC_ERROR_VC1_PICTURE_INIT (0xDEC20100) +#define NVC5B0_DEC_ERROR_VC1_STATEMACHINE_FAILURE (0xDEC20101) +#define NVC5B0_DEC_ERROR_VC1_INVALID_CTXID_PIC (0xDEC20901) +#define NVC5B0_DEC_ERROR_VC1_INVALID_CTXID_UCODE (0xDEC20902) +#define NVC5B0_DEC_ERROR_VC1_INVALID_CTXID_FC (0xDEC20903) +#define NVC5B0_DEC_ERROR_VC1_INVAILD_CTXID_SLH (0xDEC20904) +#define NVC5B0_DEC_ERROR_VC1_INVALID_UCODE_SIZE (0xDEC20905) +#define NVC5B0_DEC_ERROR_VC1_INVALID_SLICE_COUNT (0xDEC20906) +#define NVC5B0_DEC_ERROR_H264_APPTIMER_EXPIRED (0xDEC30001) +#define NVC5B0_DEC_ERROR_H264_MVTIMER_EXPIRED (0xDEC30002) +#define NVC5B0_DEC_ERROR_H264_INVALID_TOKEN (0xDEC30003) +#define NVC5B0_DEC_ERROR_H264_SLICEDATA_MISSING (0xDEC30004) +#define NVC5B0_DEC_ERROR_H264_HWERR_INTERRUPT (0xDEC30005) +#define NVC5B0_DEC_ERROR_H264_DETECTED_VLD_FAILURE (0xDEC30006) +#define NVC5B0_DEC_ERROR_H264_ERRINTSTART (0xDEC30010) +#define NVC5B0_DEC_ERROR_H264_IQT_ERRINT (0xDEC30011) +#define NVC5B0_DEC_ERROR_H264_MC_ERRINT (0xDEC30012) +#define NVC5B0_DEC_ERROR_H264_MC_IQT_ERRINT (0xDEC30013) +#define NVC5B0_DEC_ERROR_H264_REC_ERRINT (0xDEC30014) +#define NVC5B0_DEC_ERROR_H264_REC_IQT_ERRINT (0xDEC30015) +#define NVC5B0_DEC_ERROR_H264_REC_MC_ERRINT (0xDEC30016) +#define NVC5B0_DEC_ERROR_H264_REC_MC_IQT_ERRINT (0xDEC30017) +#define NVC5B0_DEC_ERROR_H264_DBF_ERRINT (0xDEC30018) +#define NVC5B0_DEC_ERROR_H264_DBF_IQT_ERRINT (0xDEC30019) +#define NVC5B0_DEC_ERROR_H264_DBF_MC_ERRINT (0xDEC3001A) +#define NVC5B0_DEC_ERROR_H264_DBF_MC_IQT_ERRINT (0xDEC3001B) +#define NVC5B0_DEC_ERROR_H264_DBF_REC_ERRINT (0xDEC3001C) +#define NVC5B0_DEC_ERROR_H264_DBF_REC_IQT_ERRINT (0xDEC3001D) +#define NVC5B0_DEC_ERROR_H264_DBF_REC_MC_ERRINT (0xDEC3001E) +#define NVC5B0_DEC_ERROR_H264_DBF_REC_MC_IQT_ERRINT (0xDEC3001F) +#define NVC5B0_DEC_ERROR_H264_PICTURE_INIT (0xDEC30100) +#define NVC5B0_DEC_ERROR_H264_STATEMACHINE_FAILURE (0xDEC30101) +#define NVC5B0_DEC_ERROR_H264_INVALID_CTXID_PIC (0xDEC30901) +#define NVC5B0_DEC_ERROR_H264_INVALID_CTXID_UCODE (0xDEC30902) +#define NVC5B0_DEC_ERROR_H264_INVALID_CTXID_FC (0xDEC30903) +#define NVC5B0_DEC_ERROR_H264_INVALID_CTXID_SLH (0xDEC30904) +#define NVC5B0_DEC_ERROR_H264_INVALID_UCODE_SIZE (0xDEC30905) +#define NVC5B0_DEC_ERROR_H264_INVALID_SLICE_COUNT (0xDEC30906) +#define NVC5B0_DEC_ERROR_MPEG4_APPTIMER_EXPIRED (0xDEC40001) +#define NVC5B0_DEC_ERROR_MPEG4_MVTIMER_EXPIRED (0xDEC40002) +#define NVC5B0_DEC_ERROR_MPEG4_INVALID_TOKEN (0xDEC40003) +#define NVC5B0_DEC_ERROR_MPEG4_SLICEDATA_MISSING (0xDEC40004) +#define NVC5B0_DEC_ERROR_MPEG4_HWERR_INTERRUPT (0xDEC40005) +#define NVC5B0_DEC_ERROR_MPEG4_DETECTED_VLD_FAILURE (0xDEC40006) +#define NVC5B0_DEC_ERROR_MPEG4_TIMEOUT_POLLING_FOR_DATA (0xDEC40007) +#define NVC5B0_DEC_ERROR_MPEG4_PDEC_PIC_END_UNALIGNED (0xDEC40008) +#define NVC5B0_DEC_ERROR_MPEG4_WDTIMER_EXPIRED (0xDEC40009) +#define NVC5B0_DEC_ERROR_MPEG4_ERRINTSTART (0xDEC40010) +#define NVC5B0_DEC_ERROR_MPEG4_IQT_ERRINT (0xDEC40011) +#define NVC5B0_DEC_ERROR_MPEG4_MC_ERRINT (0xDEC40012) +#define NVC5B0_DEC_ERROR_MPEG4_MC_IQT_ERRINT (0xDEC40013) +#define NVC5B0_DEC_ERROR_MPEG4_REC_ERRINT (0xDEC40014) +#define NVC5B0_DEC_ERROR_MPEG4_REC_IQT_ERRINT (0xDEC40015) +#define NVC5B0_DEC_ERROR_MPEG4_REC_MC_ERRINT (0xDEC40016) +#define NVC5B0_DEC_ERROR_MPEG4_REC_MC_IQT_ERRINT (0xDEC40017) +#define NVC5B0_DEC_ERROR_MPEG4_DBF_ERRINT (0xDEC40018) +#define NVC5B0_DEC_ERROR_MPEG4_DBF_IQT_ERRINT (0xDEC40019) +#define NVC5B0_DEC_ERROR_MPEG4_DBF_MC_ERRINT (0xDEC4001A) +#define NVC5B0_DEC_ERROR_MPEG4_DBF_MC_IQT_ERRINT (0xDEC4001B) +#define NVC5B0_DEC_ERROR_MPEG4_DBF_REC_ERRINT (0xDEC4001C) +#define NVC5B0_DEC_ERROR_MPEG4_DBF_REC_IQT_ERRINT (0xDEC4001D) +#define NVC5B0_DEC_ERROR_MPEG4_DBF_REC_MC_ERRINT (0xDEC4001E) +#define NVC5B0_DEC_ERROR_MPEG4_DBF_REC_MC_IQT_ERRINT (0xDEC4001F) +#define NVC5B0_DEC_ERROR_MPEG4_PICTURE_INIT (0xDEC40100) +#define NVC5B0_DEC_ERROR_MPEG4_STATEMACHINE_FAILURE (0xDEC40101) +#define NVC5B0_DEC_ERROR_MPEG4_INVALID_CTXID_PIC (0xDEC40901) +#define NVC5B0_DEC_ERROR_MPEG4_INVALID_CTXID_UCODE (0xDEC40902) +#define NVC5B0_DEC_ERROR_MPEG4_INVALID_CTXID_FC (0xDEC40903) +#define NVC5B0_DEC_ERROR_MPEG4_INVALID_CTXID_SLH (0xDEC40904) +#define NVC5B0_DEC_ERROR_MPEG4_INVALID_UCODE_SIZE (0xDEC40905) +#define NVC5B0_DEC_ERROR_MPEG4_INVALID_SLICE_COUNT (0xDEC40906) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif /* AVUTIL_CLC5B0_H */ diff --git a/libavutil/cle7d0.h b/libavutil/cle7d0.h new file mode 100644 index 0000000000..f17e67036f --- /dev/null +++ b/libavutil/cle7d0.h @@ -0,0 +1,129 @@ +/******************************************************************************* + Copyright (c) 1993-2020, NVIDIA CORPORATION. All rights reserved. + + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + +*******************************************************************************/ + +#ifndef AVUTIL_CLE7D0_H +#define AVUTIL_CLE7D0_H + +#ifdef __cplusplus +extern "C" { +#endif + +#define NVE7D0_VIDEO_NVJPG (0x0000E7D0) + +#define NVE7D0_NOP (0x00000100) +#define NVE7D0_NOP_PARAMETER 31:0 +#define NVE7D0_SET_APPLICATION_ID (0x00000200) +#define NVE7D0_SET_APPLICATION_ID_ID 31:0 +#define NVE7D0_SET_APPLICATION_ID_ID_NVJPG_DECODER (0x00000001) +#define NVE7D0_SET_APPLICATION_ID_ID_NVJPG_ENCODER (0x00000002) +#define NVE7D0_SET_WATCHDOG_TIMER (0x00000204) +#define NVE7D0_SET_WATCHDOG_TIMER_TIMER 31:0 +#define NVE7D0_SEMAPHORE_A (0x00000240) +#define NVE7D0_SEMAPHORE_A_UPPER 7:0 +#define NVE7D0_SEMAPHORE_B (0x00000244) +#define NVE7D0_SEMAPHORE_B_LOWER 31:0 +#define NVE7D0_SEMAPHORE_C (0x00000248) +#define NVE7D0_SEMAPHORE_C_PAYLOAD 31:0 +#define NVE7D0_CTX_SAVE_AREA (0x0000024C) +#define NVE7D0_CTX_SAVE_AREA_OFFSET 27:0 +#define NVE7D0_CTX_SAVE_AREA_CTX_VALID 31:28 +#define NVE7D0_CTX_SWITCH (0x00000250) +#define NVE7D0_CTX_SWITCH_RESTORE 0:0 +#define NVE7D0_CTX_SWITCH_RESTORE_FALSE (0x00000000) +#define NVE7D0_CTX_SWITCH_RESTORE_TRUE (0x00000001) +#define NVE7D0_CTX_SWITCH_RST_NOTIFY 1:1 +#define NVE7D0_CTX_SWITCH_RST_NOTIFY_FALSE (0x00000000) +#define NVE7D0_CTX_SWITCH_RST_NOTIFY_TRUE (0x00000001) +#define NVE7D0_CTX_SWITCH_RESERVED 7:2 +#define NVE7D0_CTX_SWITCH_ASID 23:8 +#define NVE7D0_EXECUTE (0x00000300) +#define NVE7D0_EXECUTE_NOTIFY 0:0 +#define NVE7D0_EXECUTE_NOTIFY_DISABLE (0x00000000) +#define NVE7D0_EXECUTE_NOTIFY_ENABLE (0x00000001) +#define NVE7D0_EXECUTE_NOTIFY_ON 1:1 +#define NVE7D0_EXECUTE_NOTIFY_ON_END (0x00000000) +#define NVE7D0_EXECUTE_NOTIFY_ON_BEGIN (0x00000001) +#define NVE7D0_EXECUTE_AWAKEN 8:8 +#define NVE7D0_EXECUTE_AWAKEN_DISABLE (0x00000000) +#define NVE7D0_EXECUTE_AWAKEN_ENABLE (0x00000001) +#define NVE7D0_SEMAPHORE_D (0x00000304) +#define NVE7D0_SEMAPHORE_D_STRUCTURE_SIZE 0:0 +#define NVE7D0_SEMAPHORE_D_STRUCTURE_SIZE_ONE (0x00000000) +#define NVE7D0_SEMAPHORE_D_STRUCTURE_SIZE_FOUR (0x00000001) +#define NVE7D0_SEMAPHORE_D_AWAKEN_ENABLE 8:8 +#define NVE7D0_SEMAPHORE_D_AWAKEN_ENABLE_FALSE (0x00000000) +#define NVE7D0_SEMAPHORE_D_AWAKEN_ENABLE_TRUE (0x00000001) +#define NVE7D0_SEMAPHORE_D_OPERATION 17:16 +#define NVE7D0_SEMAPHORE_D_OPERATION_RELEASE (0x00000000) +#define NVE7D0_SEMAPHORE_D_OPERATION_RESERVED0 (0x00000001) +#define NVE7D0_SEMAPHORE_D_OPERATION_RESERVED1 (0x00000002) +#define NVE7D0_SEMAPHORE_D_OPERATION_TRAP (0x00000003) +#define NVE7D0_SEMAPHORE_D_FLUSH_DISABLE 21:21 +#define NVE7D0_SEMAPHORE_D_FLUSH_DISABLE_FALSE (0x00000000) +#define NVE7D0_SEMAPHORE_D_FLUSH_DISABLE_TRUE (0x00000001) +#define NVE7D0_SET_CONTROL_PARAMS (0x00000700) +#define NVE7D0_SET_CONTROL_PARAMS_GPTIMER_ON 0:0 +#define NVE7D0_SET_CONTROL_PARAMS_DUMP_CYCLE_COUNT 1:1 +#define NVE7D0_SET_CONTROL_PARAMS_DEBUG_MODE 2:2 +#define NVE7D0_SET_PICTURE_INDEX (0x00000704) +#define NVE7D0_SET_PICTURE_INDEX_INDEX 31:0 +#define NVE7D0_SET_IN_DRV_PIC_SETUP (0x00000708) +#define NVE7D0_SET_IN_DRV_PIC_SETUP_OFFSET 31:0 +#define NVE7D0_SET_OUT_STATUS (0x0000070C) +#define NVE7D0_SET_OUT_STATUS_OFFSET 31:0 +#define NVE7D0_SET_BITSTREAM (0x00000710) +#define NVE7D0_SET_BITSTREAM_OFFSET 31:0 +#define NVE7D0_SET_CUR_PIC (0x00000714) +#define NVE7D0_SET_CUR_PIC_OFFSET 31:0 +#define NVE7D0_SET_CUR_PIC_CHROMA_U (0x00000718) +#define NVE7D0_SET_CUR_PIC_CHROMA_U_OFFSET 31:0 +#define NVE7D0_SET_CUR_PIC_CHROMA_V (0x0000071C) +#define NVE7D0_SET_CUR_PIC_CHROMA_V_OFFSET 31:0 + +#define NVE7D0_ERROR_NONE (0x00000000) +#define NVE7D0_OS_ERROR_EXECUTE_INSUFFICIENT_DATA (0x00000001) +#define NVE7D0_OS_ERROR_SEMAPHORE_INSUFFICIENT_DATA (0x00000002) +#define NVE7D0_OS_ERROR_INVALID_METHOD (0x00000003) +#define NVE7D0_OS_ERROR_INVALID_DMA_PAGE (0x00000004) +#define NVE7D0_OS_ERROR_UNHANDLED_INTERRUPT (0x00000005) +#define NVE7D0_OS_ERROR_EXCEPTION (0x00000006) +#define NVE7D0_OS_ERROR_INVALID_CTXSW_REQUEST (0x00000007) +#define NVE7D0_OS_ERROR_APPLICATION (0x00000008) +#define NVE7D0_OS_INTERRUPT_EXECUTE_AWAKEN (0x00000100) +#define NVE7D0_OS_INTERRUPT_BACKEND_SEMAPHORE_AWAKEN (0x00000200) +#define NVE7D0_OS_INTERRUPT_CTX_ERROR_FBIF (0x00000300) +#define NVE7D0_OS_INTERRUPT_LIMIT_VIOLATION (0x00000400) +#define NVE7D0_OS_INTERRUPT_LIMIT_AND_FBIF_CTX_ERROR (0x00000500) +#define NVE7D0_OS_INTERRUPT_HALT_ENGINE (0x00000600) +#define NVE7D0_OS_INTERRUPT_TRAP_NONSTALL (0x00000700) +#define NVE7D0_OS_INTERRUPT_CTX_SAVE_DONE (0x00000800) +#define NVE7D0_OS_INTERRUPT_CTX_RESTORE_DONE (0x00000900) +#define NVE7D0_ERROR_JPGAPPTIMER_EXPIRED (0x30000001) +#define NVE7D0_ERROR_JPGINVALID_INPUT (0x30000002) +#define NVE7D0_ERROR_JPGHWERR_INTERRUPT (0x30000003) +#define NVE7D0_ERROR_JPGBAD_MAGIC (0x30000004) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif /* AVUTIL_CLE7D0_H */ diff --git a/libavutil/nvdec_drv.h b/libavutil/nvdec_drv.h new file mode 100644 index 0000000000..7803cd16b3 --- /dev/null +++ b/libavutil/nvdec_drv.h @@ -0,0 +1,1858 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1993-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef AVUTIL_NVDEC_DRV_H +#define AVUTIL_NVDEC_DRV_H + +// TODO: Many fields can be converted to bitfields to save memory BW +// TODO: Revisit reserved fields for proper alignment and memory savings + +/////////////////////////////////////////////////////////////////////////////// +// NVDEC(MSDEC 5) is a single engine solution, and seperates into VLD, MV, IQT, +// MCFETCH, MC, MCC, REC, DBF, DFBFDMA, HIST etc unit. +// The class(driver to HW) can mainly seperate into VLD parser +// and Decoder part to be consistent with original design. And +// the sequence level info usally set in VLD part. Later codec like +// VP8 won't name in this way. +// MSVLD: Multi-Standard VLD parser. +// +#define ALIGN_UP(v, n) (((v) + ((n)-1)) &~ ((n)-1)) +#define NVDEC_ALIGN(value) ALIGN_UP(value,256) // Align to 256 bytes +#define NVDEC_MAX_MPEG2_SLICE 65536 // at 4096*4096, macroblock count = 65536, 1 macroblock per slice + +#define NVDEC_CODEC_MPEG1 0 +#define NVDEC_CODEC_MPEG2 1 +#define NVDEC_CODEC_VC1 2 +#define NVDEC_CODEC_H264 3 +#define NVDEC_CODEC_MPEG4 4 +#define NVDEC_CODEC_DIVX NVDEC_CODEC_MPEG4 +#define NVDEC_CODEC_VP8 5 +#define NVDEC_CODEC_HEVC 7 +#define NVDEC_CODEC_VP9 9 +#define NVDEC_CODEC_HEVC_PARSER 12 +#define NVDEC_CODEC_AV1 10 + +// AES encryption +enum +{ + AES128_NONE = 0x0, + AES128_CTR = 0x1, + AES128_CBC, + AES128_ECB, + AES128_OFB, + AES128_CTR_LSB16B, + AES128_CLR_AS_ENCRYPT, + AES128_RESERVED = 0x7 +}; + +enum +{ + AES128_CTS_DISABLE = 0x0, + AES128_CTS_ENABLE = 0x1 +}; + +enum +{ + AES128_PADDING_NONE = 0x0, + AES128_PADDING_CARRY_OVER, + AES128_PADDING_RFC2630, + AES128_PADDING_RESERVED = 0x7 +}; + +typedef enum +{ + ENCR_MODE_CTR64 = 0, + ENCR_MODE_CBC = 1, + ENCR_MODE_ECB = 2, + ENCR_MODE_ECB_PARTIAL = 3, + ENCR_MODE_CBC_PARTIAL = 4, + ENCR_MODE_CLEAR_INTO_VPR = 5, // used for clear stream decoding into VPR. + ENCR_MODE_FORCE_INTO_VPR = 6, // used to force decode output into VPR. +} ENCR_MODE; + +// drm_mode configuration +// +// Bit 0:2 AES encryption mode +// Bit 3 CTS (CipherTextStealing) enable/disable +// Bit 4:6 Padding type +// Bit 7:7 Unwrap key enable/disable + +#define AES_MODE_MASK 0x7 +#define AES_CTS_MASK 0x1 +#define AES_PADDING_TYPE_MASK 0x7 +#define AES_UNWRAP_KEY_MASK 0x1 + +#define AES_MODE_SHIFT 0 +#define AES_CTS_SHIFT 3 +#define AES_PADDING_TYPE_SHIFT 4 +#define AES_UNWRAP_KEY_SHIFT 7 + +#define AES_SET_FLAG(M, C, P) ((M & AES_MODE_MASK) << AES_MODE_SHIFT) | \ + ((C & AES_CTS_MASK) << AES_CTS_SHIFT) | \ + ((P & AES_PADDING_TYPE_MASK) << AES_PADDING_TYPE_SHIFT) + +#define AES_GET_FLAG(V, F) ((V & ((AES_##F##_MASK) <<(AES_##F##_SHIFT))) >> (AES_##F##_SHIFT)) + +#define DRM_MODE_MASK 0x7f // Bits 0:6 (0:2 -> AES_MODE, 3 -> AES_CTS, 4:6 -> AES_PADDING_TYPE) +#define AES_GET_DRM_MODE(V) (V & DRM_MODE_MASK) + +enum { DRM_MS_PIFF_CTR = AES_SET_FLAG(AES128_CTR, AES128_CTS_DISABLE, AES128_PADDING_CARRY_OVER) }; +enum { DRM_MS_PIFF_CBC = AES_SET_FLAG(AES128_CBC, AES128_CTS_DISABLE, AES128_PADDING_NONE) }; +enum { DRM_MARLIN_CTR = AES_SET_FLAG(AES128_CTR, AES128_CTS_DISABLE, AES128_PADDING_NONE) }; +enum { DRM_MARLIN_CBC = AES_SET_FLAG(AES128_CBC, AES128_CTS_DISABLE, AES128_PADDING_RFC2630) }; +enum { DRM_WIDEVINE = AES_SET_FLAG(AES128_CBC, AES128_CTS_ENABLE, AES128_PADDING_NONE) }; +enum { DRM_WIDEVINE_CTR = AES_SET_FLAG(AES128_CTR, AES128_CTS_DISABLE, AES128_PADDING_CARRY_OVER) }; +enum { DRM_ULTRA_VIOLET = AES_SET_FLAG(AES128_CTR_LSB16B, AES128_CTS_DISABLE, AES128_PADDING_NONE) }; +enum { DRM_NONE = AES_SET_FLAG(AES128_NONE, AES128_CTS_DISABLE, AES128_PADDING_NONE) }; +enum { DRM_CLR_AS_ENCRYPT = AES_SET_FLAG(AES128_CLR_AS_ENCRYPT, AES128_CTS_DISABLE, AES128_PADDING_NONE)}; + +// SSM entry structure +typedef struct _nvdec_ssm_s { + unsigned int bytes_of_protected_data;//bytes of protected data, follows bytes_of_clear_data. Note: When padding is enabled, it does not include the padding_bytes (1~15), which can be derived by "(16-(bytes_of_protected_data&0xF))&0xF" + unsigned int bytes_of_clear_data:16; //bytes of clear data, located before bytes_of_protected_data + unsigned int skip_byte_blk : 4; //valid when (entry_type==0 && mode = 1) + unsigned int crypt_byte_blk : 4; //valid when (entry_type==0 && mode = 1) + unsigned int skip : 1; //whether this SSM entry should be skipped or not + unsigned int last : 1; //whether this SSM entry is the last one for the whole decoding frame + unsigned int pad : 1; //valid when (entry_type==0 && mode==0 && AES_PADDING_TYPE==AES128_PADDING_RFC2630), 0 for pad_end, 1 for pad_begin + unsigned int mode : 1; //0 for normal mode, 1 for pattern mode + unsigned int entry_type : 1; //0 for DATA, 1 for IV + unsigned int reserved : 3; +} nvdec_ssm_s; /* SubSampleMap, 8bytes */ + +// PASS2 OTF extension structure for SSM support, not exist in nvdec_mpeg4_pic_s (as MPEG4 OTF SW-DRM is not supported yet) +typedef struct _nvdec_pass2_otf_ext_s { + unsigned int ssm_entry_num :16; //specifies how many SSM entries (each in unit of 8 bytes) existed in SET_SUB_SAMPLE_MAP_OFFSET surface + unsigned int ssm_iv_num :16; //specifies how many SSM IV (each in unit of 16 bytes) existed in SET_SUB_SAMPLE_MAP_IV_OFFSET surface + unsigned int real_stream_length; //the real stream length, which is the bitstream length EMD/VLD will get after whole frame SSM processing, sum up of "clear+protected" bytes in SSM entries and removing "non_slice_data/skip". + unsigned int non_slice_data :16; //specifies the first many bytes needed to skip, includes only those of "clear+protected" bytes ("padding" bytes excluded) + unsigned int drm_mode : 7; + unsigned int reserved : 9; +} nvdec_pass2_otf_ext_s; /* 12bytes */ + + +//NVDEC5.0 low latency decoding (partial stream kickoff without context switch), method will reuse HevcSetSliceInfoBufferOffset. +typedef struct _nvdec_substream_entry_s { + unsigned int substream_start_offset; //substream byte start offset to bitstream base address + unsigned int substream_length; //subsream length in byte + unsigned int substream_first_tile_idx : 8; //the first tile index(raster scan in frame) of this substream,max is 255 + unsigned int substream_last_tile_idx : 8; //the last tile index(raster scan in frame) of this substream, max is 255 + unsigned int last_substream_entry_in_frame : 1; //this entry is the last substream entry of this frame + unsigned int reserved : 15; +} nvdec_substream_entry_s;/*low latency without context switch substream entry map,12bytes*/ + + +// GIP + +/* tile border coefficients of filter */ +#define GIP_ASIC_VERT_FILTER_RAM_SIZE 16 /* bytes per pixel */ + +/* BSD control data of current picture at tile border + * 11 * 128 bits per 4x4 tile = 128/(8*4) bytes per row */ +#define GIP_ASIC_BSD_CTRL_RAM_SIZE 4 /* bytes per row */ + +/* 8 dc + 8 to boundary + 6*16 + 2*6*64 + 2*64 -> 63 * 16 bytes */ +#define GIP_ASIC_SCALING_LIST_SIZE (16*64) + +/* tile border coefficients of filter */ +#define GIP_ASIC_VERT_SAO_RAM_SIZE 16 /* bytes per pixel */ + +/* max number of tiles times width and height (2 bytes each), + * rounding up to next 16 bytes boundary + one extra 16 byte + * chunk (HW guys wanted to have this) */ +#define GIP_ASIC_TILE_SIZE ((20*22*2*2+16+15) & ~0xF) + +/* Segment map uses 32 bytes / CTB */ +#define GIP_ASIC_VP9_CTB_SEG_SIZE 32 + +// HEVC Filter FG buffer +#define HEVC_DBLK_TOP_SIZE_IN_SB16 ALIGN_UP(632, 128) // ctb16 + 444 +#define HEVC_DBLK_TOP_BUF_SIZE(w) NVDEC_ALIGN( (ALIGN_UP(w,16)/16 + 2) * HEVC_DBLK_TOP_SIZE_IN_SB16) // 8K: 1285*256 + +#define HEVC_DBLK_LEFT_SIZE_IN_SB16 ALIGN_UP(506, 128) // ctb16 + 444 +#define HEVC_DBLK_LEFT_BUF_SIZE(h) NVDEC_ALIGN( (ALIGN_UP(h,16)/16 + 2) * HEVC_DBLK_LEFT_SIZE_IN_SB16) // 8K: 1028*256 + +#define HEVC_SAO_LEFT_SIZE_IN_SB16 ALIGN_UP(713, 128) // ctb16 + 444 +#define HEVC_SAO_LEFT_BUF_SIZE(h) NVDEC_ALIGN( (ALIGN_UP(h,16)/16 + 2) * HEVC_SAO_LEFT_SIZE_IN_SB16) // 8K: 1542*256 + +// VP9 Filter FG buffer +#define VP9_DBLK_TOP_SIZE_IN_SB64 ALIGN_UP(2000, 128) // 420 +#define VP9_DBLK_TOP_BUF_SIZE(w) NVDEC_ALIGN( (ALIGN_UP(w,64)/64 + 2) * VP9_DBLK_TOP_SIZE_IN_SB64) // 8K: 1040*256 + +#define VP9_DBLK_LEFT_SIZE_IN_SB64 ALIGN_UP(1600, 128) // 420 +#define VP9_DBLK_LEFT_BUF_SIZE(h) NVDEC_ALIGN( (ALIGN_UP(h,64)/64 + 2) * VP9_DBLK_LEFT_SIZE_IN_SB64) // 8K: 845*256 + +// VP9 Hint Dump Buffer +#define VP9_HINT_DUMP_SIZE_IN_SB64 ((64*64)/(4*4)*8) // 8 bytes per CU, 256 CUs(2048 bytes) per SB64 +#define VP9_HINT_DUMP_SIZE(w, h) NVDEC_ALIGN(VP9_HINT_DUMP_SIZE_IN_SB64*((w+63)/64)*((h+63)/64)) + +// used for ecdma debug +typedef struct _nvdec_ecdma_config_s +{ + unsigned int ecdma_enable; // enable/disable ecdma + unsigned short ecdma_blk_x_src; // src start position x , it's 64x aligned + unsigned short ecdma_blk_y_src; // src start position y , it's 8x aligned + unsigned short ecdma_blk_x_dst; // dst start position x , it's 64x aligned + unsigned short ecdma_blk_y_dst; // dst start position y , it's 8x aligned + unsigned short ref_pic_idx; // ref(src) picture index , used to derived source picture base address + unsigned short boundary0_top; // src insided tile/partition region top boundary + unsigned short boundary0_bottom; // src insided tile/partition region bottom boundary + unsigned short boundary1_left; // src insided tile/partition region left boundary + unsigned short boundary1_right; // src insided tile/partition region right boundary + unsigned char blk_copy_flag; // blk_copy enable flag. + // if it's 1 ,ctb_size ==3,ecdma_blk_x_src == boundary1_left and ecdma_blk_y_src == boundary0_top ; + // if it's 0 ,ecdma_blk_x_src == ecdma_blk_x_dst and ecdma_blk_y_src == ecdma_blk_y_dst; + unsigned char ctb_size; // ctb_size .0:64x64,1:32x32,2:16x16,3:8x8 +} nvdec_ecdma_config_s; + +typedef struct _nvdec_status_hevc_s +{ + unsigned int frame_status_intra_cnt; //Intra block counter, in unit of 8x8 block, IPCM block included + unsigned int frame_status_inter_cnt; //Inter block counter, in unit of 8x8 block, SKIP block included + unsigned int frame_status_skip_cnt; //Skip block counter, in unit of 4x4 block, blocks having NO/ZERO texture/coeff data + unsigned int frame_status_fwd_mvx_cnt; //ABS sum of forward MVx, one 14bit MVx(integer) per 4x4 block + unsigned int frame_status_fwd_mvy_cnt; //ABS sum of forward MVy, one 14bit MVy(integer) per 4x4 block + unsigned int frame_status_bwd_mvx_cnt; //ABS sum of backward MVx, one 14bit MVx(integer) per 4x4 block + unsigned int frame_status_bwd_mvy_cnt; //ABS sum of backward MVy, one 14bit MVy(integer) per 4x4 block + unsigned int error_ctb_pos; //[15:0] error ctb position in Y direction, [31:16] error ctb position in X direction + unsigned int error_slice_pos; //[15:0] error slice position in Y direction, [31:16] error slice position in X direction +} nvdec_status_hevc_s; + +typedef struct _nvdec_status_vp9_s +{ + unsigned int frame_status_intra_cnt; //Intra block counter, in unit of 8x8 block, IPCM block included + unsigned int frame_status_inter_cnt; //Inter block counter, in unit of 8x8 block, SKIP block included + unsigned int frame_status_skip_cnt; //Skip block counter, in unit of 4x4 block, blocks having NO/ZERO texture/coeff data + unsigned int frame_status_fwd_mvx_cnt; //ABS sum of forward MVx, one 14bit MVx(integer) per 4x4 block + unsigned int frame_status_fwd_mvy_cnt; //ABS sum of forward MVy, one 14bit MVy(integer) per 4x4 block + unsigned int frame_status_bwd_mvx_cnt; //ABS sum of backward MVx, one 14bit MVx(integer) per 4x4 block + unsigned int frame_status_bwd_mvy_cnt; //ABS sum of backward MVy, one 14bit MVy(integer) per 4x4 block + unsigned int error_ctb_pos; //[15:0] error ctb position in Y direction, [31:16] error ctb position in X direction + unsigned int error_slice_pos; //[15:0] error slice position in Y direction, [31:16] error slice position in X direction +} nvdec_status_vp9_s; + +typedef struct _nvdec_status_s +{ + unsigned int mbs_correctly_decoded; // total numers of correctly decoded macroblocks + unsigned int mbs_in_error; // number of error macroblocks. + unsigned int cycle_count; // total cycles taken for execute. read from PERF_DECODE_FRAME_V register + unsigned int error_status; // report error if any + union + { + nvdec_status_hevc_s hevc; + nvdec_status_vp9_s vp9; + }; + unsigned int slice_header_error_code; // report error in slice header + +} nvdec_status_s; + +// per 16x16 block, used in hevc/vp9 surface of SetExternalMVBufferOffset when error_external_mv_en = 1 +typedef struct _external_mv_s +{ + int mvx : 14; //integrate pixel precision + int mvy : 14; //integrate pixel precision + unsigned int refidx : 4; +} external_mv_s; + +// HEVC +typedef struct _nvdec_hevc_main10_444_ext_s +{ + unsigned int transformSkipRotationEnableFlag : 1; //sps extension for transform_skip_rotation_enabled_flag + unsigned int transformSkipContextEnableFlag : 1; //sps extension for transform_skip_context_enabled_flag + unsigned int intraBlockCopyEnableFlag :1; //sps intraBlockCopyEnableFlag, always 0 before spec define it + unsigned int implicitRdpcmEnableFlag : 1; //sps implicit_rdpcm_enabled_flag + unsigned int explicitRdpcmEnableFlag : 1; //sps explicit_rdpcm_enabled_flag + unsigned int extendedPrecisionProcessingFlag : 1; //sps extended_precision_processing_flag,always 0 in current profile + unsigned int intraSmoothingDisabledFlag : 1; //sps intra_smoothing_disabled_flag + unsigned int highPrecisionOffsetsEnableFlag :1; //sps high_precision_offsets_enabled_flag + unsigned int fastRiceAdaptationEnableFlag: 1; //sps fast_rice_adaptation_enabled_flag + unsigned int cabacBypassAlignmentEnableFlag : 1; //sps cabac_bypass_alignment_enabled_flag, always 0 in current profile + unsigned int sps_444_extension_reserved : 22; //sps reserve for future extension + + unsigned int log2MaxTransformSkipSize : 4 ; //pps extension log2_max_transform_skip_block_size_minus2, 0...5 + unsigned int crossComponentPredictionEnableFlag: 1; //pps cross_component_prediction_enabled_flag + unsigned int chromaQpAdjustmentEnableFlag:1; //pps chroma_qp_adjustment_enabled_flag + unsigned int diffCuChromaQpAdjustmentDepth:2; //pps diff_cu_chroma_qp_adjustment_depth, 0...3 + unsigned int chromaQpAdjustmentTableSize:3; //pps chroma_qp_adjustment_table_size_minus1+1, 1...6 + unsigned int log2SaoOffsetScaleLuma:3; //pps log2_sao_offset_scale_luma, max(0,bitdepth-10),maxBitdepth 16 for future. + unsigned int log2SaoOffsetScaleChroma: 3; //pps log2_sao_offset_scale_chroma + unsigned int pps_444_extension_reserved : 15; //pps reserved + char cb_qp_adjustment[6]; //-[12,+12] + char cr_qp_adjustment[6]; //-[12,+12] + unsigned int HevcFltAboveOffset; // filter above offset respect to filter buffer, 256 bytes unit + unsigned int HevcSaoAboveOffset; // sao above offset respect to filter buffer, 256 bytes unit +} nvdec_hevc_main10_444_ext_s; + +typedef struct _nvdec_hevc_pic_v1_s +{ + // New fields + //hevc main10 444 extensions + nvdec_hevc_main10_444_ext_s hevc_main10_444_ext; + + //HEVC skip bytes from beginning setting for secure + //it is different to the sw_hdr_skip_length who skips the middle of stream of + //the slice header which is parsed by driver + unsigned int sw_skip_start_length : 14; + unsigned int external_ref_mem_dis : 1; + unsigned int error_recovery_start_pos : 2; //0: from start of frame, 1: from start of slice segment, 2: from error detected ctb, 3: reserved + unsigned int error_external_mv_en : 1; + unsigned int reserved0 : 14; + // Reserved bits padding +} nvdec_hevc_pic_v1_s; + +//No versioning in structure: NVDEC2 (T210 and GM206) +//version v1 : NVDEC3 (T186 and GP100) +//version v2 : NVDEC3.1 (GP10x) + +typedef struct _nvdec_hevc_pic_v2_s +{ + // mv-hevc field + unsigned int mv_hevc_enable :1; + unsigned int nuh_layer_id :6; + unsigned int default_ref_layers_active_flag :1; + unsigned int NumDirectRefLayers :6; + unsigned int max_one_active_ref_layer_flag :1; + unsigned int NumActiveRefLayerPics :6; + unsigned int poc_lsb_not_present_flag :1; + unsigned int reserved0 :10; +} nvdec_hevc_pic_v2_s; + +typedef struct _nvdec_hevc_pic_v3_s +{ + // slice level decoding + unsigned int slice_decoding_enable:1;//1: enable slice level decoding + unsigned int slice_ec_enable:1; //1: enable slice error concealment. When slice_ec_enable=1,slice_decoding_enable must be 1; + unsigned int slice_ec_mv_type:2; //0: zero mv; 1: co-located mv; 2: external mv; + unsigned int err_detected_sw:1; //1: indicate sw/driver has detected error already in frame kick mode + unsigned int slice_ec_slice_type:2; //0: B slice; 1: P slice ; others: reserved + unsigned int slice_strm_recfg_en:1; //enable slice bitstream re-configure or not ; + unsigned int reserved:24; + unsigned int HevcSliceEdgeOffset;// slice edge buffer offset which repsect to filter buffer ,256 bytes as one unit +}nvdec_hevc_pic_v3_s; + +typedef struct _nvdec_hevc_pic_s +{ + //The key/IV addr must be 128bit alignment + unsigned int wrapped_session_key[4]; //session keys + unsigned int wrapped_content_key[4]; //content keys + unsigned int initialization_vector[4]; //Ctrl64 initial vector + // hevc_bitstream_data_info + unsigned int stream_len; // stream length in one frame + unsigned int enable_encryption; // flag to enable/disable encryption + unsigned int key_increment : 6; // added to content key after unwrapping + unsigned int encryption_mode : 4; + unsigned int key_slot_index : 4; + unsigned int ssm_en : 1; + unsigned int enable_histogram : 1; // histogram stats output enable + unsigned int enable_substream_decoding: 1; //frame substream kickoff without context switch + unsigned int reserved0 :15; + + // Driver may or may not use based upon need. + // If 0 then default value of 1<<27 = 298ms @ 450MHz will be used in ucode. + // Driver can send this value based upon resolution using the formula: + // gptimer_timeout_value = 3 * (cycles required for one frame) + unsigned int gptimer_timeout_value; + + // general + unsigned char tileformat : 2 ; // 0: TBL; 1: KBL; 2: Tile16x16 + unsigned char gob_height : 3 ; // Set GOB height, 0: GOB_2, 1: GOB_4, 2: GOB_8, 3: GOB_16, 4: GOB_32 (NVDEC3 onwards) + unsigned char reserverd_surface_format : 3 ; + unsigned char sw_start_code_e; // 0: stream doesn't contain start codes,1: stream contains start codes + unsigned char disp_output_mode; // 0: Rec.709 8 bit, 1: Rec.709 10 bit, 2: Rec.709 10 bits -> 8 bit, 3: Rec.2020 10 bit -> 8 bit + unsigned char reserved1; + unsigned int framestride[2]; // frame buffer stride for luma and chroma + unsigned int colMvBuffersize; // collocated MV buffer size of one picture ,256 bytes unit + unsigned int HevcSaoBufferOffset; // sao buffer offset respect to filter buffer ,256 bytes unit . + unsigned int HevcBsdCtrlOffset; // bsd buffer offset respect to filter buffer ,256 bytes unit . + // sps + unsigned short pic_width_in_luma_samples; // :15, 48(?)..16384, multiple of 8 (48 is smallest width supported by NVDEC for CTU size 16x16) + unsigned short pic_height_in_luma_samples; // :15, 8..16384, multiple of 8 + unsigned int chroma_format_idc : 4; // always 1 (=4:2:0) + unsigned int bit_depth_luma : 4; // 8..12 + unsigned int bit_depth_chroma : 4; + unsigned int log2_min_luma_coding_block_size : 4; // 3..6 + unsigned int log2_max_luma_coding_block_size : 4; // 3..6 + unsigned int log2_min_transform_block_size : 4; // 2..5 + unsigned int log2_max_transform_block_size : 4; // 2..5 + unsigned int reserved2 : 4; + + unsigned int max_transform_hierarchy_depth_inter : 3; // 0..4 + unsigned int max_transform_hierarchy_depth_intra : 3; // 0..4 + unsigned int scalingListEnable : 1; // + unsigned int amp_enable_flag : 1; // + unsigned int sample_adaptive_offset_enabled_flag : 1; // + unsigned int pcm_enabled_flag : 1; // + unsigned int pcm_sample_bit_depth_luma : 4; // + unsigned int pcm_sample_bit_depth_chroma : 4; + unsigned int log2_min_pcm_luma_coding_block_size : 4; // + unsigned int log2_max_pcm_luma_coding_block_size : 4; // + unsigned int pcm_loop_filter_disabled_flag : 1; // + unsigned int sps_temporal_mvp_enabled_flag : 1; // + unsigned int strong_intra_smoothing_enabled_flag : 1; // + unsigned int reserved3 : 3; + // pps + unsigned int dependent_slice_segments_enabled_flag : 1; // + unsigned int output_flag_present_flag : 1; // + unsigned int num_extra_slice_header_bits : 3; // 0..7 (normally 0) + unsigned int sign_data_hiding_enabled_flag : 1; // + unsigned int cabac_init_present_flag : 1; // + unsigned int num_ref_idx_l0_default_active : 4; // 1..15 + unsigned int num_ref_idx_l1_default_active : 4; // 1..15 + unsigned int init_qp : 7; // 0..127, support higher bitdepth + unsigned int constrained_intra_pred_flag : 1; // + unsigned int transform_skip_enabled_flag : 1; // + unsigned int cu_qp_delta_enabled_flag : 1; // + unsigned int diff_cu_qp_delta_depth : 2; // 0..3 + unsigned int reserved4 : 5; // + + char pps_cb_qp_offset ; // -12..12 + char pps_cr_qp_offset ; // -12..12 + char pps_beta_offset ; // -12..12 + char pps_tc_offset ; // -12..12 + unsigned int pps_slice_chroma_qp_offsets_present_flag : 1; // + unsigned int weighted_pred_flag : 1; // + unsigned int weighted_bipred_flag : 1; // + unsigned int transquant_bypass_enabled_flag : 1; // + unsigned int tiles_enabled_flag : 1; // (redundant: = num_tile_columns_minus1!=0 || num_tile_rows_minus1!=0) + unsigned int entropy_coding_sync_enabled_flag : 1; // + unsigned int num_tile_columns : 5; // 0..20 + unsigned int num_tile_rows : 5; // 0..22 + unsigned int loop_filter_across_tiles_enabled_flag : 1; // + unsigned int loop_filter_across_slices_enabled_flag : 1; // + unsigned int deblocking_filter_control_present_flag : 1; // + unsigned int deblocking_filter_override_enabled_flag : 1; // + unsigned int pps_deblocking_filter_disabled_flag : 1; // + unsigned int lists_modification_present_flag : 1; // + unsigned int log2_parallel_merge_level : 3; // 2..4 + unsigned int slice_segment_header_extension_present_flag : 1; // (normally 0) + unsigned int reserved5 : 6; + + // reference picture related + unsigned char num_ref_frames; + unsigned char reserved6; + unsigned short longtermflag; // long term flag for refpiclist.bit 15 for picidx 0, bit 14 for picidx 1,... + unsigned char initreflistidxl0[16]; // :5, [refPicidx] 0..15 + unsigned char initreflistidxl1[16]; // :5, [refPicidx] 0..15 + short RefDiffPicOrderCnts[16]; // poc diff between current and reference pictures .[-128,127] + // misc + unsigned char IDR_picture_flag; // idr flag for current picture + unsigned char RAP_picture_flag; // rap flag for current picture + unsigned char curr_pic_idx; // current picture store buffer index,used to derive the store addess of frame buffer and MV + unsigned char pattern_id; // used for dithering to select between 2 tables + unsigned short sw_hdr_skip_length; // reference picture inititial related syntax elements(SE) bits in slice header. + // those SE only decoding once in driver,related bits will flush in HW + unsigned short reserved7; + + // used for ecdma debug + nvdec_ecdma_config_s ecdma_cfg; + + //DXVA on windows + unsigned int separate_colour_plane_flag : 1; + unsigned int log2_max_pic_order_cnt_lsb_minus4 : 4; //0~12 + unsigned int num_short_term_ref_pic_sets : 7 ; //0~64 + unsigned int num_long_term_ref_pics_sps : 6; //0~32 + unsigned int bBitParsingDisable : 1 ; //disable parsing + unsigned int num_delta_pocs_of_rps_idx : 8; + unsigned int long_term_ref_pics_present_flag : 1; + unsigned int reserved_dxva : 4; + //the number of bits for short_term_ref_pic_set()in slice header,dxva API + unsigned int num_bits_short_term_ref_pics_in_slice; + + // New additions + nvdec_hevc_pic_v1_s v1; + nvdec_hevc_pic_v2_s v2; + nvdec_hevc_pic_v3_s v3; + nvdec_pass2_otf_ext_s ssm; + +} nvdec_hevc_pic_s; + +//hevc slice info class +typedef struct _hevc_slice_info_s { + unsigned int first_flag :1;//first slice(s) of frame,must valid for slice EC + unsigned int err_flag :1;//error slice(s) .optional info for EC + unsigned int last_flag :1;//last slice segment(s) of frame,this bit is must be valid when slice_strm_recfg_en==1 or slice_ec==1 + unsigned int conceal_partial_slice :1; // indicate do partial slice error conealment for packet loss case + unsigned int available :1; // indicate the slice bitstream is available. + unsigned int reserved0 :7; + unsigned int ctb_count :20;// ctbs counter inside slice(s) .must valid for slice EC + unsigned int bs_offset; //slice(s) bitstream offset in bitstream buffer (in byte unit) + unsigned int bs_length; //slice(s) bitstream length. It is sum of aligned size and skip size and valid slice bitstream size. + unsigned short start_ctbx; //slice start ctbx ,it's optional,HW can output it in previous slice decoding. + //but this is one check points for error + unsigned short start_ctby; //slice start ctby + } hevc_slice_info_s; + + +//hevc slice ctx class +//slice pos and next slice address +typedef struct _slice_edge_ctb_pos_ctx_s { + unsigned int next_slice_pos_ctbxy; //2d address in raster scan + unsigned int next_slice_segment_addr; //1d address in tile scan +}slice_edge_ctb_pos_ctx_s; + +// next slice's first ctb located tile related information +typedef struct _slice_edge_tile_ctx_s { + unsigned int tileInfo1;// Misc tile info includes tile width and tile height and tile col and tile row + unsigned int tileInfo2;// Misc tile info includes tile start ctbx and start ctby and tile index + unsigned int tileInfo3;// Misc tile info includes ctb pos inside tile +} slice_edge_tile_ctx_s; + +//frame level stats +typedef struct _slice_edge_stats_ctx_s { + unsigned int frame_status_intra_cnt;// frame stats for intra block count + unsigned int frame_status_inter_cnt;// frame stats for inter block count + unsigned int frame_status_skip_cnt;// frame stats for skip block count + unsigned int frame_status_fwd_mvx_cnt;// frame stats for sum of abs fwd mvx + unsigned int frame_status_fwd_mvy_cnt;// frame stats for sum of abs fwd mvy + unsigned int frame_status_bwd_mvx_cnt;// frame stats for sum of abs bwd mvx + unsigned int frame_status_bwd_mvy_cnt;// frame stats for sum of abs bwd mvy + unsigned int frame_status_mv_cnt_ext;// extension bits of sum of abs mv to keep full precision. +}slice_edge_stats_ctx_s; + +//ctx of vpc_edge unit for tile left +typedef struct _slice_vpc_edge_ctx_s { + unsigned int reserved; +}slice_vpc_edge_ctx_s; + +//ctx of vpc_main unit +typedef struct _slice_vpc_main_ctx_s { + unsigned int reserved; +} slice_vpc_main_ctx_s; + +//hevc slice edge ctx class +typedef struct _slice_edge_ctx_s { + //ctb pos + slice_edge_ctb_pos_ctx_s slice_ctb_pos_ctx; + // stats + slice_edge_stats_ctx_s slice_stats_ctx; + // tile info + slice_edge_tile_ctx_s slice_tile_ctx; + //vpc_edge + slice_vpc_edge_ctx_s slice_vpc_edge_ctx; + //vpc_main + slice_vpc_main_ctx_s slice_vpc_main_ctx; +} slice_edge_ctx_s; + +typedef struct _nvdec_hevc_scaling_list_s { + unsigned char ScalingListDCCoeff16x16[6]; + unsigned char ScalingListDCCoeff32x32[2]; + unsigned char reserved0[8]; + + unsigned char ScalingList4x4[6][16]; + unsigned char ScalingList8x8[6][64]; + unsigned char ScalingList16x16[6][64]; + unsigned char ScalingList32x32[2][64]; +} nvdec_hevc_scaling_list_s; + + +//vp9 + +typedef struct _nvdec_vp9_pic_v1_s +{ + // New fields + // new_var : xx; // for variables with expanded bitlength, comment on why the new bit legth is required + // Reserved bits for padding and/or non-HW specific functionality + unsigned int Vp9FltAboveOffset; // filter above offset respect to filter buffer, 256 bytes unit + unsigned int external_ref_mem_dis : 1; + unsigned int bit_depth : 4; + unsigned int error_recovery_start_pos : 2; //0: from start of frame, 1: from start of slice segment, 2: from error detected ctb, 3: reserved + unsigned int error_external_mv_en : 1; + unsigned int Reserved0 : 24; +} nvdec_vp9_pic_v1_s; + +enum VP9_FRAME_SFC_ID +{ + VP9_LAST_FRAME_SFC = 0, + VP9_GOLDEN_FRAME_SFC, + VP9_ALTREF_FRAME_SFC, + VP9_CURR_FRAME_SFC +}; + +typedef struct _nvdec_vp9_pic_s +{ + // vp9_bitstream_data_info + //Key and IV address must 128bit alignment + unsigned int wrapped_session_key[4]; //session keys + unsigned int wrapped_content_key[4]; //content keys + unsigned int initialization_vector[4]; //Ctrl64 initial vector + unsigned int stream_len; // stream length in one frame + unsigned int enable_encryption; // flag to enable/disable encryption + unsigned int key_increment : 6; // added to content key after unwrapping + unsigned int encryption_mode : 4; + unsigned int sw_hdr_skip_length :14; //vp9 skip bytes setting for secure + unsigned int key_slot_index : 4; + unsigned int ssm_en : 1; + unsigned int enable_histogram : 1; // histogram stats output enable + unsigned int reserved0 : 2; + + // Driver may or may not use based upon need. + // If 0 then default value of 1<<27 = 298ms @ 450MHz will be used in ucode. + // Driver can send this value based upon resolution using the formula: + // gptimer_timeout_value = 3 * (cycles required for one frame) + unsigned int gptimer_timeout_value; + + //general + unsigned char tileformat : 2 ; // 0: TBL; 1: KBL; 2: Tile16x16 + unsigned char gob_height : 3 ; // Set GOB height, 0: GOB_2, 1: GOB_4, 2: GOB_8, 3: GOB_16, 4: GOB_32 (NVDEC3 onwards) + unsigned char reserverd_surface_format : 3 ; + unsigned char reserved1[3]; + unsigned int Vp9BsdCtrlOffset; // bsd buffer offset respect to filter buffer ,256 bytes unit . + + + //ref_last dimensions + unsigned short ref0_width; //ref_last coded width + unsigned short ref0_height; //ref_last coded height + unsigned short ref0_stride[2]; //ref_last stride + + //ref_golden dimensions + unsigned short ref1_width; //ref_golden coded width + unsigned short ref1_height; //ref_golden coded height + unsigned short ref1_stride[2]; //ref_golden stride + + //ref_alt dimensions + unsigned short ref2_width; //ref_alt coded width + unsigned short ref2_height; //ref_alt coded height + unsigned short ref2_stride[2]; //ref_alt stride + + + /* Current frame dimensions */ + unsigned short width; //pic width + unsigned short height; //pic height + unsigned short framestride[2]; // frame buffer stride for luma and chroma + + unsigned char keyFrame :1; + unsigned char prevIsKeyFrame:1; + unsigned char resolutionChange:1; + unsigned char errorResilient:1; + unsigned char prevShowFrame:1; + unsigned char intraOnly:1; + unsigned char reserved2 : 2; + + /* DCT coefficient partitions */ + //unsigned int offsetToDctParts; + + unsigned char reserved3[3]; + //unsigned char activeRefIdx[3];//3 bits + //unsigned char refreshFrameFlags; + //unsigned char refreshEntropyProbs; + //unsigned char frameParallelDecoding; + //unsigned char resetFrameContext; + + unsigned char refFrameSignBias[4]; + char loopFilterLevel;//6 bits + char loopFilterSharpness;//3 bits + + /* Quantization parameters */ + unsigned char qpYAc; + char qpYDc; + char qpChAc; + char qpChDc; + + /* From here down, frame-to-frame persisting stuff */ + + char lossless; + char transform_mode; + char allow_high_precision_mv; + char mcomp_filter_type; + char comp_pred_mode; + char comp_fixed_ref; + char comp_var_ref[2]; + char log2_tile_columns; + char log2_tile_rows; + + /* Segment and macroblock specific values */ + unsigned char segmentEnabled; + unsigned char segmentMapUpdate; + unsigned char segmentMapTemporalUpdate; + unsigned char segmentFeatureMode; /* ABS data or delta data */ + unsigned char segmentFeatureEnable[8][4]; + short segmentFeatureData[8][4]; + char modeRefLfEnabled; + char mbRefLfDelta[4]; + char mbModeLfDelta[2]; + char reserved5; // for alignment + + // New additions + nvdec_vp9_pic_v1_s v1; + nvdec_pass2_otf_ext_s ssm; + +} nvdec_vp9_pic_s; + +#define NVDEC_VP9HWPAD(x, y) unsigned char x[y] + +typedef struct { + /* last bytes of address 41 */ + unsigned char joints[3]; + unsigned char sign[2]; + /* address 42 */ + unsigned char class0[2][1]; + unsigned char fp[2][3]; + unsigned char class0_hp[2]; + unsigned char hp[2]; + unsigned char classes[2][10]; + /* address 43 */ + unsigned char class0_fp[2][2][3]; + unsigned char bits[2][10]; + +} nvdec_nmv_context; + +typedef struct { + unsigned int joints[4]; + unsigned int sign[2][2]; + unsigned int classes[2][11]; + unsigned int class0[2][2]; + unsigned int bits[2][10][2]; + unsigned int class0_fp[2][2][4]; + unsigned int fp[2][4]; + unsigned int class0_hp[2][2]; + unsigned int hp[2][2]; + +} nvdec_nmv_context_counts; + +/* Adaptive entropy contexts, padding elements are added to have + * 256 bit aligned tables for HW access. + * Compile with TRACE_PROB_TABLES to print bases for each table. */ +typedef struct nvdec_vp9AdaptiveEntropyProbs_s +{ + /* address 32 */ + unsigned char inter_mode_prob[7][4]; + unsigned char intra_inter_prob[4]; + + /* address 33 */ + unsigned char uv_mode_prob[10][8]; + unsigned char tx8x8_prob[2][1]; + unsigned char tx16x16_prob[2][2]; + unsigned char tx32x32_prob[2][3]; + unsigned char sb_ymode_probB[4][1]; + unsigned char sb_ymode_prob[4][8]; + + /* address 37 */ + unsigned char partition_prob[2][16][4]; + + /* address 41 */ + unsigned char uv_mode_probB[10][1]; + unsigned char switchable_interp_prob[4][2]; + unsigned char comp_inter_prob[5]; + unsigned char mbskip_probs[3]; + NVDEC_VP9HWPAD(pad1, 1); + + nvdec_nmv_context nmvc; + + /* address 44 */ + unsigned char single_ref_prob[5][2]; + unsigned char comp_ref_prob[5]; + NVDEC_VP9HWPAD(pad2, 17); + + /* address 45 */ + unsigned char probCoeffs[2][2][6][6][4]; + unsigned char probCoeffs8x8[2][2][6][6][4]; + unsigned char probCoeffs16x16[2][2][6][6][4]; + unsigned char probCoeffs32x32[2][2][6][6][4]; + +} nvdec_vp9AdaptiveEntropyProbs_t; + +/* Entropy contexts */ +typedef struct nvdec_vp9EntropyProbs_s +{ + /* Default keyframe probs */ + /* Table formatted for 256b memory, probs 0to7 for all tables followed by + * probs 8toN for all tables. + * Compile with TRACE_PROB_TABLES to print bases for each table. */ + + unsigned char kf_bmode_prob[10][10][8]; + + /* Address 25 */ + unsigned char kf_bmode_probB[10][10][1]; + unsigned char ref_pred_probs[3]; + unsigned char mb_segment_tree_probs[7]; + unsigned char segment_pred_probs[3]; + unsigned char ref_scores[4]; + unsigned char prob_comppred[2]; + NVDEC_VP9HWPAD(pad1, 9); + + /* Address 29 */ + unsigned char kf_uv_mode_prob[10][8]; + unsigned char kf_uv_mode_probB[10][1]; + NVDEC_VP9HWPAD(pad2, 6); + + nvdec_vp9AdaptiveEntropyProbs_t a; /* Probs with backward adaptation */ + +} nvdec_vp9EntropyProbs_t; + +/* Counters for adaptive entropy contexts */ +typedef struct nvdec_vp9EntropyCounts_s +{ + unsigned int inter_mode_counts[7][3][2]; + unsigned int sb_ymode_counts[4][10]; + unsigned int uv_mode_counts[10][10]; + unsigned int partition_counts[16][4]; + unsigned int switchable_interp_counts[4][3]; + unsigned int intra_inter_count[4][2]; + unsigned int comp_inter_count[5][2]; + unsigned int single_ref_count[5][2][2]; + unsigned int comp_ref_count[5][2]; + unsigned int tx32x32_count[2][4]; + unsigned int tx16x16_count[2][3]; + unsigned int tx8x8_count[2][2]; + unsigned int mbskip_count[3][2]; + + nvdec_nmv_context_counts nmvcount; + + unsigned int countCoeffs[2][2][6][6][4]; + unsigned int countCoeffs8x8[2][2][6][6][4]; + unsigned int countCoeffs16x16[2][2][6][6][4]; + unsigned int countCoeffs32x32[2][2][6][6][4]; + + unsigned int countEobs[4][2][2][6][6]; + +} nvdec_vp9EntropyCounts_t; + +// Legacy codecs encryption parameters +typedef struct _nvdec_pass2_otf_s { + unsigned int wrapped_session_key[4]; // session keys + unsigned int wrapped_content_key[4]; // content keys + unsigned int initialization_vector[4];// Ctrl64 initial vector + unsigned int enable_encryption : 1; // flag to enable/disable encryption + unsigned int key_increment : 6; // added to content key after unwrapping + unsigned int encryption_mode : 4; + unsigned int key_slot_index : 4; + unsigned int ssm_en : 1; + unsigned int reserved1 :16; // reserved +} nvdec_pass2_otf_s; // 0x10 bytes + +typedef struct _nvdec_display_param_s +{ + unsigned int enableTFOutput : 1; //=1, enable dbfdma to output the display surface; if disable, then the following configure on tf is useless. + //remap for VC1 + unsigned int VC1MapYFlag : 1; + unsigned int MapYValue : 3; + unsigned int VC1MapUVFlag : 1; + unsigned int MapUVValue : 3; + //tf + unsigned int OutStride : 8; + unsigned int TilingFormat : 3; + unsigned int OutputStructure : 1; //(0=frame, 1=field) + unsigned int reserved0 :11; + int OutputTop[2]; // in units of 256 + int OutputBottom[2]; // in units of 256 + //histogram + unsigned int enableHistogram : 1; // enable histogram info collection. + unsigned int HistogramStartX :12; // start X of Histogram window + unsigned int HistogramStartY :12; // start Y of Histogram window + unsigned int reserved1 : 7; + unsigned int HistogramEndX :12; // end X of Histogram window + unsigned int HistogramEndY :12; // end y of Histogram window + unsigned int reserved2 : 8; +} nvdec_display_param_s; // size 0x1c bytes + +// H.264 +typedef struct _nvdec_dpb_entry_s // 16 bytes +{ + unsigned int index : 7; // uncompressed frame buffer index + unsigned int col_idx : 5; // index of associated co-located motion data buffer + unsigned int state : 2; // bit1(state)=1: top field used for reference, bit1(state)=1: bottom field used for reference + unsigned int is_long_term : 1; // 0=short-term, 1=long-term + unsigned int not_existing : 1; // 1=marked as non-existing + unsigned int is_field : 1; // set if unpaired field or complementary field pair + unsigned int top_field_marking : 4; + unsigned int bottom_field_marking : 4; + unsigned int output_memory_layout : 1; // Set according to picture level output NV12/NV24 setting. + unsigned int reserved : 6; + unsigned int FieldOrderCnt[2]; // : 2*32 [top/bottom] + int FrameIdx; // : 16 short-term: FrameNum (16 bits), long-term: LongTermFrameIdx (4 bits) +} nvdec_dpb_entry_s; + +typedef struct _nvdec_h264_pic_s +{ + nvdec_pass2_otf_s encryption_params; + unsigned char eos[16]; + unsigned char explicitEOSPresentFlag; + unsigned char hint_dump_en; //enable COLOMV surface dump for all frames, which includes hints of "MV/REFIDX/QP/CBP/MBPART/MBTYPE", nvbug: 200212874 + unsigned char reserved0[2]; + unsigned int stream_len; + unsigned int slice_count; + unsigned int mbhist_buffer_size; // to pass buffer size of MBHIST_BUFFER + + // Driver may or may not use based upon need. + // If 0 then default value of 1<<27 = 298ms @ 450MHz will be used in ucode. + // Driver can send this value based upon resolution using the formula: + // gptimer_timeout_value = 3 * (cycles required for one frame) + unsigned int gptimer_timeout_value; + + // Fields from msvld_h264_seq_s + int log2_max_pic_order_cnt_lsb_minus4; + int delta_pic_order_always_zero_flag; + int frame_mbs_only_flag; + int PicWidthInMbs; + int FrameHeightInMbs; + + unsigned int tileFormat : 2 ; // 0: TBL; 1: KBL; 2: Tile16x16 + unsigned int gob_height : 3 ; // Set GOB height, 0: GOB_2, 1: GOB_4, 2: GOB_8, 3: GOB_16, 4: GOB_32 (NVDEC3 onwards) + unsigned int reserverd_surface_format : 27; + + // Fields from msvld_h264_pic_s + int entropy_coding_mode_flag; + int pic_order_present_flag; + int num_ref_idx_l0_active_minus1; + int num_ref_idx_l1_active_minus1; + int deblocking_filter_control_present_flag; + int redundant_pic_cnt_present_flag; + int transform_8x8_mode_flag; + + // Fields from mspdec_h264_picture_setup_s + unsigned int pitch_luma; // Luma pitch + unsigned int pitch_chroma; // chroma pitch + + unsigned int luma_top_offset; // offset of luma top field in units of 256 + unsigned int luma_bot_offset; // offset of luma bottom field in units of 256 + unsigned int luma_frame_offset; // offset of luma frame in units of 256 + unsigned int chroma_top_offset; // offset of chroma top field in units of 256 + unsigned int chroma_bot_offset; // offset of chroma bottom field in units of 256 + unsigned int chroma_frame_offset; // offset of chroma frame in units of 256 + unsigned int HistBufferSize; // in units of 256 + + unsigned int MbaffFrameFlag : 1; // + unsigned int direct_8x8_inference_flag: 1; // + unsigned int weighted_pred_flag : 1; // + unsigned int constrained_intra_pred_flag:1; // + unsigned int ref_pic_flag : 1; // reference picture (nal_ref_idc != 0) + unsigned int field_pic_flag : 1; // + unsigned int bottom_field_flag : 1; // + unsigned int second_field : 1; // second field of complementary reference field + unsigned int log2_max_frame_num_minus4: 4; // (0..12) + unsigned int chroma_format_idc : 2; // + unsigned int pic_order_cnt_type : 2; // (0..2) + int pic_init_qp_minus26 : 6; // : 6 (-26..+25) + int chroma_qp_index_offset : 5; // : 5 (-12..+12) + int second_chroma_qp_index_offset : 5; // : 5 (-12..+12) + + unsigned int weighted_bipred_idc : 2; // : 2 (0..2) + unsigned int CurrPicIdx : 7; // : 7 uncompressed frame buffer index + unsigned int CurrColIdx : 5; // : 5 index of associated co-located motion data buffer + unsigned int frame_num : 16; // + unsigned int frame_surfaces : 1; // frame surfaces flag + unsigned int output_memory_layout : 1; // 0: NV12; 1:NV24. Field pair must use the same setting. + + int CurrFieldOrderCnt[2]; // : 32 [Top_Bottom], [0]=TopFieldOrderCnt, [1]=BottomFieldOrderCnt + nvdec_dpb_entry_s dpb[16]; + unsigned char WeightScale[6][4][4]; // : 6*4*4*8 in raster scan order (not zig-zag order) + unsigned char WeightScale8x8[2][8][8]; // : 2*8*8*8 in raster scan order (not zig-zag order) + + // mvc setup info, must be zero if not mvc + unsigned char num_inter_view_refs_lX[2]; // number of inter-view references + char reserved1[14]; // reserved for alignment + signed char inter_view_refidx_lX[2][16]; // DPB indices (must also be marked as long-term) + + // lossless decode (At the time of writing this manual, x264 and JM encoders, differ in Intra_8x8 reference sample filtering) + unsigned int lossless_ipred8x8_filter_enable : 1; // = 0, skips Intra_8x8 reference sample filtering, for vertical and horizontal predictions (x264 encoded streams); = 1, filter Intra_8x8 reference samples (JM encoded streams) + unsigned int qpprime_y_zero_transform_bypass_flag : 1; // determines the transform bypass mode + unsigned int reserved2 : 30; // kept for alignment; may be used for other parameters + + nvdec_display_param_s displayPara; + nvdec_pass2_otf_ext_s ssm; + +} nvdec_h264_pic_s; + +// VC-1 Scratch buffer +typedef enum _vc1_fcm_e +{ + FCM_PROGRESSIVE = 0, + FCM_FRAME_INTERLACE = 2, + FCM_FIELD_INTERLACE = 3 +} vc1_fcm_e; + +typedef enum _syntax_vc1_ptype_e +{ + PTYPE_I = 0, + PTYPE_P = 1, + PTYPE_B = 2, + PTYPE_BI = 3, //PTYPE_BI is not used to config register NV_CNVDEC_VLD_PIC_INFO_COMMON. field NV_CNVDEC_VLD_PIC_INFO_COMMON_PIC_CODING_VC1 is only 2 bits. I and BI pictures are configured with same value. Please refer to manual. + PTYPE_SKIPPED = 4 +} syntax_vc1_ptype_e; + +// 7.1.1.32, Table 46 etc. +enum vc1_mvmode_e +{ + MVMODE_MIXEDMV = 0, + MVMODE_1MV = 1, + MVMODE_1MV_HALFPEL = 2, + MVMODE_1MV_HALFPEL_BILINEAR = 3, + MVMODE_INTENSITY_COMPENSATION = 4 +}; + +// 9.1.1.42, Table 105 +typedef enum _vc1_fptype_e +{ + FPTYPE_I_I = 0, + FPTYPE_I_P, + FPTYPE_P_I, + FPTYPE_P_P, + FPTYPE_B_B, + FPTYPE_B_BI, + FPTYPE_BI_B, + FPTYPE_BI_BI +} vc1_fptype_e; + +// Table 43 (7.1.1.31.2) +typedef enum _vc1_dqprofile_e +{ + DQPROFILE_ALL_FOUR_EDGES_ = 0, + DQPROFILE_DOUBLE_EDGE_ = 1, + DQPROFILE_SINGLE_EDGE_ = 2, + DQPROFILE_ALL_MACROBLOCKS_ = 3 +} vc1_dqprofile_e; + +typedef struct _nvdec_vc1_pic_s +{ + nvdec_pass2_otf_s encryption_params; + unsigned char eos[16]; // to pass end of stream data separately if not present in bitstream surface + unsigned char prefixStartCode[4]; // used for dxva to pass prefix start code. + unsigned int bitstream_offset; // offset in words from start of bitstream surface if there is gap. + unsigned char explicitEOSPresentFlag; // to indicate that eos[] is used for passing end of stream data. + unsigned char reserved0[3]; + unsigned int stream_len; + unsigned int slice_count; + unsigned int scratch_pic_buffer_size; + + // Driver may or may not use based upon need. + // If 0 then default value of 1<<27 = 298ms @ 450MHz will be used in ucode. + // Driver can send this value based upon resolution using the formula: + // gptimer_timeout_value = 3 * (cycles required for one frame) + unsigned int gptimer_timeout_value; + + // Fields from vc1_seq_s + unsigned short FrameWidth; // actual frame width + unsigned short FrameHeight; // actual frame height + + unsigned char profile; // 1 = SIMPLE or MAIN, 2 = ADVANCED + unsigned char postprocflag; + unsigned char pulldown; + unsigned char interlace; + + unsigned char tfcntrflag; + unsigned char finterpflag; + unsigned char psf; + unsigned char tileFormat : 2 ; // 0: TBL; 1: KBL; 2: Tile16x16 + unsigned char gob_height : 3 ; // Set GOB height, 0: GOB_2, 1: GOB_4, 2: GOB_8, 3: GOB_16, 4: GOB_32 (NVDEC3 onwards) + unsigned char reserverd_surface_format : 3 ; + + // simple,main + unsigned char multires; + unsigned char syncmarker; + unsigned char rangered; + unsigned char maxbframes; + + // Fields from vc1_entrypoint_s + unsigned char dquant; + unsigned char panscan_flag; + unsigned char refdist_flag; + unsigned char quantizer; + + unsigned char extended_mv; + unsigned char extended_dmv; + unsigned char overlap; + unsigned char vstransform; + + // Fields from vc1_scratch_s + char refdist; + char reserved1[3]; // for alignment + + // Fields from vld_vc1_pic_s + vc1_fcm_e fcm; + syntax_vc1_ptype_e ptype; + int tfcntr; + int rptfrm; + int tff; + int rndctrl; + int pqindex; + int halfqp; + int pquantizer; + int postproc; + int condover; + int transacfrm; + int transacfrm2; + int transdctab; + int pqdiff; + int abspq; + int dquantfrm; + vc1_dqprofile_e dqprofile; + int dqsbedge; + int dqdbedge; + int dqbilevel; + int mvrange; + enum vc1_mvmode_e mvmode; + enum vc1_mvmode_e mvmode2; + int lumscale; + int lumshift; + int mvtab; + int cbptab; + int ttmbf; + int ttfrm; + int bfraction; + vc1_fptype_e fptype; + int numref; + int reffield; + int dmvrange; + int intcompfield; + int lumscale1; // type was char in ucode + int lumshift1; // type was char in ucode + int lumscale2; // type was char in ucode + int lumshift2; // type was char in ucode + int mbmodetab; + int imvtab; + int icbptab; + int fourmvbptab; + int fourmvswitch; + int intcomp; + int twomvbptab; + // simple,main + int rangeredfrm; + + // Fields from pdec_vc1_pic_s + unsigned int HistBufferSize; // in units of 256 + // frame buffers + unsigned int FrameStride[2]; // [y_c] + unsigned int luma_top_offset; // offset of luma top field in units of 256 + unsigned int luma_bot_offset; // offset of luma bottom field in units of 256 + unsigned int luma_frame_offset; // offset of luma frame in units of 256 + unsigned int chroma_top_offset; // offset of chroma top field in units of 256 + unsigned int chroma_bot_offset; // offset of chroma bottom field in units of 256 + unsigned int chroma_frame_offset; // offset of chroma frame in units of 256 + + unsigned short CodedWidth; // entrypoint specific + unsigned short CodedHeight; // entrypoint specific + + unsigned char loopfilter; // entrypoint specific + unsigned char fastuvmc; // entrypoint specific + unsigned char output_memory_layout; // picture specific + unsigned char ref_memory_layout[2]; // picture specific 0: fwd, 1: bwd + unsigned char reserved3[3]; // for alignment + + nvdec_display_param_s displayPara; + nvdec_pass2_otf_ext_s ssm; + +} nvdec_vc1_pic_s; + +// MPEG-2 +typedef struct _nvdec_mpeg2_pic_s +{ + nvdec_pass2_otf_s encryption_params; + unsigned char eos[16]; + unsigned char explicitEOSPresentFlag; + unsigned char reserved0[3]; + unsigned int stream_len; + unsigned int slice_count; + + // Driver may or may not use based upon need. + // If 0 then default value of 1<<27 = 298ms @ 450MHz will be used in ucode. + // Driver can send this value based upon resolution using the formula: + // gptimer_timeout_value = 3 * (cycles required for one frame) + unsigned int gptimer_timeout_value; + + // Fields from vld_mpeg2_seq_pic_info_s + short FrameWidth; // actual frame width + short FrameHeight; // actual frame height + unsigned char picture_structure; // 0 => Reserved, 1 => Top field, 2 => Bottom field, 3 => Frame picture. Table 6-14. + unsigned char picture_coding_type; // 0 => Forbidden, 1 => I, 2 => P, 3 => B, 4 => D (for MPEG-2). Table 6-12. + unsigned char intra_dc_precision; // 0 => 8 bits, 1=> 9 bits, 2 => 10 bits, 3 => 11 bits. Table 6-13. + char frame_pred_frame_dct; // as in section 6.3.10 + char concealment_motion_vectors; // as in section 6.3.10 + char intra_vlc_format; // as in section 6.3.10 + unsigned char tileFormat : 2 ; // 0: TBL; 1: KBL; 2: Tile16x16 + unsigned char gob_height : 3 ; // Set GOB height, 0: GOB_2, 1: GOB_4, 2: GOB_8, 3: GOB_16, 4: GOB_32 (NVDEC3 onwards) + unsigned char reserverd_surface_format : 3 ; + + char reserved1; // always 0 + char f_code[4]; // as in section 6.3.10 + + // Fields from pdec_mpeg2_picture_setup_s + unsigned short PicWidthInMbs; + unsigned short FrameHeightInMbs; + unsigned int pitch_luma; + unsigned int pitch_chroma; + unsigned int luma_top_offset; + unsigned int luma_bot_offset; + unsigned int luma_frame_offset; + unsigned int chroma_top_offset; + unsigned int chroma_bot_offset; + unsigned int chroma_frame_offset; + unsigned int HistBufferSize; + unsigned short output_memory_layout; + unsigned short alternate_scan; + unsigned short secondfield; + /******************************/ + // Got rid of the union kept for compatibility with NVDEC1. + // Removed field mpeg2, and kept rounding type. + // NVDEC1 ucode is not using the mpeg2 field, instead using codec type from the methods. + // Rounding type should only be set for Divx3.11. + unsigned short rounding_type; + /******************************/ + unsigned int MbInfoSizeInBytes; + unsigned int q_scale_type; + unsigned int top_field_first; + unsigned int full_pel_fwd_vector; + unsigned int full_pel_bwd_vector; + unsigned char quant_mat_8x8intra[64]; + unsigned char quant_mat_8x8nonintra[64]; + unsigned int ref_memory_layout[2]; //0:for fwd; 1:for bwd + + nvdec_display_param_s displayPara; + nvdec_pass2_otf_ext_s ssm; + +} nvdec_mpeg2_pic_s; + +// MPEG-4 +typedef struct _nvdec_mpeg4_pic_s +{ + nvdec_pass2_otf_s encryption_params; + unsigned char eos[16]; + unsigned char explicitEOSPresentFlag; + unsigned char reserved2[3]; // for alignment + unsigned int stream_len; + unsigned int slice_count; + unsigned int scratch_pic_buffer_size; + + // Driver may or may not use based upon need. + // If 0 then default value of 1<<27 = 298ms @ 450MHz will be used in ucode. + // Driver can send this value based upon resolution using the formula: + // gptimer_timeout_value = 3 * (cycles required for one frame) + unsigned int gptimer_timeout_value; + + // Fields from vld_mpeg4_seq_s + short FrameWidth; // :13 video_object_layer_width + short FrameHeight; // :13 video_object_layer_height + char vop_time_increment_bitcount; // : 5 1..16 + char resync_marker_disable; // : 1 + unsigned char tileFormat : 2 ; // 0: TBL; 1: KBL; 2: Tile16x16 + unsigned char gob_height : 3 ; // Set GOB height, 0: GOB_2, 1: GOB_4, 2: GOB_8, 3: GOB_16, 4: GOB_32 (NVDEC3 onwards) + unsigned char reserverd_surface_format : 3 ; + char reserved3; // for alignment + + // Fields from pdec_mpeg4_picture_setup_s + int width; // : 13 + int height; // : 13 + + unsigned int FrameStride[2]; // [y_c] + unsigned int luma_top_offset; // offset of luma top field in units of 256 + unsigned int luma_bot_offset; // offset of luma bottom field in units of 256 + unsigned int luma_frame_offset; // offset of luma frame in units of 256 + unsigned int chroma_top_offset; // offset of chroma top field in units of 256 + unsigned int chroma_bot_offset; // offset of chroma bottom field in units of 256 + unsigned int chroma_frame_offset; // offset of chroma frame in units of 256 + + unsigned int HistBufferSize; // in units of 256, History buffer size + + int trd[2]; // : 16, temporal reference frame distance (only needed for B-VOPs) + int trb[2]; // : 16, temporal reference B-VOP distance from fwd reference frame (only needed for B-VOPs) + + int divx_flags; // : 16 (bit 0: DivX interlaced chroma rounding, bit 1: Divx 4 boundary padding, bit 2: Divx IDCT) + + short vop_fcode_forward; // : 1...7 + short vop_fcode_backward; // : 1...7 + + unsigned char interlaced; // : 1 + unsigned char quant_type; // : 1 + unsigned char quarter_sample; // : 1 + unsigned char short_video_header; // : 1 + + unsigned char curr_output_memory_layout; // : 1 0:NV12; 1:NV24 + unsigned char ptype; // picture type: 0 for PTYPE_I, 1 for PTYPE_P, 2 for PTYPE_B, 3 for PTYPE_BI, 4 for PTYPE_SKIPPED + unsigned char rnd; // : 1, rounding mode + unsigned char alternate_vertical_scan_flag; // : 1 + + unsigned char top_field_flag; // : 1 + unsigned char reserved0[3]; // alignment purpose + + unsigned char intra_quant_mat[64]; // : 64*8 + unsigned char nonintra_quant_mat[64]; // : 64*8 + unsigned char ref_memory_layout[2]; //0:for fwd; 1:for bwd + unsigned char reserved1[34]; // 256 byte alignemnt till now + + nvdec_display_param_s displayPara; + +} nvdec_mpeg4_pic_s; + +// VP8 +enum VP8_FRAME_TYPE +{ + VP8_KEYFRAME = 0, + VP8_INTERFRAME = 1 +}; + +enum VP8_FRAME_SFC_ID +{ + VP8_GOLDEN_FRAME_SFC = 0, + VP8_ALTREF_FRAME_SFC, + VP8_LAST_FRAME_SFC, + VP8_CURR_FRAME_SFC +}; + +typedef struct _nvdec_vp8_pic_s +{ + nvdec_pass2_otf_s encryption_params; + + // Driver may or may not use based upon need. + // If 0 then default value of 1<<27 = 298ms @ 450MHz will be used in ucode. + // Driver can send this value based upon resolution using the formula: + // gptimer_timeout_value = 3 * (cycles required for one frame) + unsigned int gptimer_timeout_value; + + unsigned short FrameWidth; // actual frame width + unsigned short FrameHeight; // actual frame height + + unsigned char keyFrame; // 1: key frame; 0: not + unsigned char version; + unsigned char tileFormat : 2 ; // 0: TBL; 1: KBL; 2: Tile16x16 + unsigned char gob_height : 3 ; // Set GOB height, 0: GOB_2, 1: GOB_4, 2: GOB_8, 3: GOB_16, 4: GOB_32 (NVDEC3 onwards) + unsigned char reserverd_surface_format : 3 ; + unsigned char errorConcealOn; // 1: error conceal on; 0: off + + unsigned int firstPartSize; // the size of first partition(frame header and mb header partition) + + // ctx + unsigned int HistBufferSize; // in units of 256 + unsigned int VLDBufferSize; // in units of 1 + // current frame buffers + unsigned int FrameStride[2]; // [y_c] + unsigned int luma_top_offset; // offset of luma top field in units of 256 + unsigned int luma_bot_offset; // offset of luma bottom field in units of 256 + unsigned int luma_frame_offset; // offset of luma frame in units of 256 + unsigned int chroma_top_offset; // offset of chroma top field in units of 256 + unsigned int chroma_bot_offset; // offset of chroma bottom field in units of 256 + unsigned int chroma_frame_offset; // offset of chroma frame in units of 256 + + nvdec_display_param_s displayPara; + + // decode picture buffere related + char current_output_memory_layout; + char output_memory_layout[3]; // output NV12/NV24 setting. item 0:golden; 1: altref; 2: last + + unsigned char segmentation_feature_data_update; + unsigned char reserved1[3]; + + // ucode return result + unsigned int resultValue; // ucode return the picture header info; includes copy_buffer_to_golden etc. + unsigned int partition_offset[8]; // byte offset to each token partition (used for encrypted streams only) + + nvdec_pass2_otf_ext_s ssm; + +} nvdec_vp8_pic_s; // size is 0xc0 + +// PASS1 + +//Sample means the entire frame is encrypted with a single IV, and subsample means a given frame may be encrypted in multiple chunks with different IVs. +#define NUM_SUBSAMPLES 32 + +typedef struct _bytes_of_data_s +{ + unsigned int clear_bytes; // clear bytes per subsample + unsigned int encypted_bytes; // encrypted bytes per subsample + +} bytes_of_data_s; + +typedef struct _nvdec_pass1_input_data_s +{ + bytes_of_data_s sample_size[NUM_SUBSAMPLES]; // clear/encrypted bytes per subsample + unsigned int initialization_vector[NUM_SUBSAMPLES][4]; // Ctrl64 initial vector per subsample + unsigned char IvValid[NUM_SUBSAMPLES]; // each element will tell whether IV is valid for that subsample or not. + unsigned int stream_len; // encrypted bitstream size. + unsigned int clearBufferSize; // allocated size of clear buffer size + unsigned int reencryptBufferSize; // allocated size of reencrypted buffer size + unsigned int vp8coeffPartitonBufferSize; // allocated buffer for vp8 coeff partition buffer + unsigned int PrevWidth; // required for VP9 + unsigned int num_nals :16; // number of subsamples in a frame + unsigned int drm_mode : 8; // DRM mode + unsigned int key_sel : 4; // key select from keyslot + unsigned int codec : 4; // codecs selection + unsigned int TotalSizeOfClearData; // Used with Pattern based encryption + unsigned int SliceHdrOffset; // This is used with pattern mode encryption where data before slice hdr comes in clear. + unsigned int EncryptBlkCnt :16; + unsigned int SkipBlkCnt :16; +} nvdec_pass1_input_data_s; + +#define VP8_MAX_TOKEN_PARTITIONS 8 +#define VP9_MAX_FRAMES_IN_SUPERFRAME 8 + +typedef struct _nvdec_pass1_output_data_s +{ + unsigned int clear_header_size; // h264/vc1/mpeg2/vp8, decrypted pps/sps/part of slice header info, 128 bits aligned + unsigned int reencrypt_data_size; // h264/vc1/mpeg2, slice level data, vp8 mb header info, 128 bits aligned + unsigned int clear_token_data_size; // vp8, clear token data saved in VPR, 128 bits aligned + unsigned int key_increment : 6; // added to content key after unwrapping + unsigned int encryption_mode : 4; // encryption mode + unsigned int bReEncrypted : 1; // set to 0 if no re-encryption is done. + unsigned int bvp9SuperFrame : 1; // set to 1 for vp9 superframe + unsigned int vp9NumFramesMinus1 : 3; // set equal to numFrames-1 for vp9superframe. Max 8 frames are possible in vp9 superframe. + unsigned int reserved1 :17; // reserved, 32 bit alignment + unsigned int wrapped_session_key[4]; // session keys + unsigned int wrapped_content_key[4]; // content keys + unsigned int initialization_vector[4]; // Ctrl64 initial vector + union { + unsigned int partition_size[VP8_MAX_TOKEN_PARTITIONS]; // size of each token partition (used for encrypted streams of VP8) + unsigned int vp9_frame_sizes[VP9_MAX_FRAMES_IN_SUPERFRAME]; // frame size information for all frames in vp9 superframe. + }; + unsigned int vp9_clear_hdr_size[VP9_MAX_FRAMES_IN_SUPERFRAME]; // clear header size for each frame in vp9 superframe. +} nvdec_pass1_output_data_s; + + +/***************************************************** + AV1 +*****************************************************/ +typedef struct _scale_factors_reference_s{ + short x_scale_fp; // horizontal fixed point scale factor + short y_scale_fp; // vertical fixed point scale factor +}scale_factors_reference_s; + +typedef struct _frame_info_t{ + unsigned short width; // in pixel, av1 support arbitray resolution + unsigned short height; + unsigned short stride[2]; // luma and chroma stride in 16Bytes + unsigned int frame_buffer_idx; // TBD :clean associate the reference frame and frame buffer id to lookup base_addr +} frame_info_t; + +typedef struct _ref_frame_struct_s{ + frame_info_t info; + scale_factors_reference_s sf; // scalefactor for reference frame and current frame size, driver can calculate it + unsigned char sign_bias : 1; // calcuate based on frame_offset and current frame offset + unsigned char wmtype : 2; // global motion parameters : identity,translation,rotzoom,affine + unsigned char reserved_rf : 5; + short frame_off; // relative offset to current frame + short roffset; // relative offset from current frame +} ref_frame_struct_s; + +typedef struct _av1_fgs_cfg_t{ + //from AV1 spec 5.9.30 Film Grain Params syntax + unsigned short apply_grain : 1; + unsigned short overlap_flag : 1; + unsigned short clip_to_restricted_range : 1; + unsigned short chroma_scaling_from_luma : 1; + unsigned short num_y_points_b : 1; // flag indicates num_y_points>0 + unsigned short num_cb_points_b : 1; // flag indicates num_cb_points>0 + unsigned short num_cr_points_b : 1; // flag indicates num_cr_points>0 + unsigned short scaling_shift : 4; + unsigned short reserved_fgs : 5; + unsigned short sw_random_seed; + short cb_offset; + short cr_offset; + char cb_mult; + char cb_luma_mult; + char cr_mult; + char cr_luma_mult; +} av1_fgs_cfg_t; + + +typedef struct _nvdec_av1_pic_s +{ + nvdec_pass2_otf_s encryption_params; + + nvdec_pass2_otf_ext_s ssm; + + av1_fgs_cfg_t fgs_cfg; + + // Driver may or may not use based upon need. + // If 0 then default value of 1<<27 = 298ms @ 450MHz will be used in ucode. + // Driver can send this value based upon resolution using the formula: + // gptimer_timeout_value = 3 * (cycles required for one frame) + unsigned int gptimer_timeout_value; + + unsigned int stream_len; // stream length. + unsigned int reserved12; // skip bytes length to real frame data . + + //sequence header + unsigned int use_128x128_superblock : 1; // superblock 128x128 or 64x64, 0:64x64, 1: 128x128 + unsigned int chroma_format : 2; // 1:420, others:reserved for future + unsigned int bit_depth : 4; // bitdepth + unsigned int enable_filter_intra : 1; // tool enable in seq level, 0 : disable 1: frame header control + unsigned int enable_intra_edge_filter : 1; + unsigned int enable_interintra_compound : 1; + unsigned int enable_masked_compound : 1; + unsigned int enable_dual_filter : 1; // enable or disable vertical and horiz filter selection + unsigned int reserved10 : 1; // 0 - disable order hint, and related tools + unsigned int reserved0 : 3; + unsigned int enable_jnt_comp : 1; // 0 - disable joint compound modes + unsigned int reserved1 : 1; + unsigned int enable_cdef : 1; + unsigned int reserved11 : 1; + unsigned int enable_fgs : 1; + unsigned int enable_substream_decoding : 1; //enable frame substream kickoff mode without context switch + unsigned int reserved2 : 10; // reserved bits + + //frame header + unsigned int frame_type : 2; // 0:Key frame, 1:Inter frame, 2:intra only, 3:s-frame + unsigned int show_frame : 1; // show frame flag + unsigned int reserved13 : 1; + unsigned int disable_cdf_update : 1; // disable CDF update during symbol decoding + unsigned int allow_screen_content_tools : 1; // screen content tool enable + unsigned int cur_frame_force_integer_mv : 1; // AMVR enable + unsigned int scale_denom_minus9 : 3; // The denominator minus9 of the superres scale + unsigned int allow_intrabc : 1; // IBC enable + unsigned int allow_high_precision_mv : 1; // 1/8 precision mv enable + unsigned int interp_filter : 3; // interpolation filter : EIGHTTAP_REGULAR,.... + unsigned int switchable_motion_mode : 1; // 0: simple motion mode, 1: SIMPLE, OBMC, LOCAL WARP + unsigned int use_ref_frame_mvs : 1; // 1: current frame can use the previous frame mv information, MFMV + unsigned int refresh_frame_context : 1; // backward update flag + unsigned int delta_q_present_flag : 1; // quantizer index delta values are present in the block level + unsigned int delta_q_res : 2; // left shift will apply to decoded quantizer index delta values + unsigned int delta_lf_present_flag : 1; // specified whether loop filter delta values are present in the block level + unsigned int delta_lf_res : 2; // specifies the left shift will apply to decoded loop filter values + unsigned int delta_lf_multi : 1; // seperate loop filter deltas for Hy,Vy,U,V edges + unsigned int reserved3 : 1; + unsigned int coded_lossless : 1; // 1 means all segments use lossless coding. Frame is fully lossless, CDEF/DBF will disable + unsigned int tile_enabled : 1; // tile enable + unsigned int reserved4 : 2; + unsigned int superres_is_scaled : 1; // frame level frame for using_superres + unsigned int reserved_fh : 1; + + unsigned int tile_cols : 8; // horizontal tile numbers in frame, max is 64 + unsigned int tile_rows : 8; // vertical tile numbers in frame, max is 64 + unsigned int context_update_tile_id : 16; // which tile cdf will be seleted as the backward update CDF, MAXTILEROW=64, MAXTILECOL=64, 12bits + + unsigned int cdef_damping_minus_3 : 2; // controls the amount of damping in the deringing filter + unsigned int cdef_bits : 2; // the number of bits needed to specify which CDEF filter to apply + unsigned int frame_tx_mode : 3; // 0:ONLY4x4,3:LARGEST,4:SELECT + unsigned int frame_reference_mode : 2; // single,compound,select + unsigned int skip_mode_flag : 1; // skip mode + unsigned int skip_ref0 : 4; + unsigned int skip_ref1 : 4; + unsigned int allow_warp : 1; // sequence level & frame level warp enable + unsigned int reduced_tx_set_used : 1; // whether the frame is restricted to oa reduced subset of the full set of transform types + unsigned int ref_scaling_enable : 1; + unsigned int reserved5 : 1; + unsigned int reserved6 : 10; // reserved bits + unsigned short superres_upscaled_width; // upscale width, frame_size_with_refs() syntax,restoration will use it + unsigned short superres_luma_step; + unsigned short superres_chroma_step; + unsigned short superres_init_luma_subpel_x; + unsigned short superres_init_chroma_subpel_x; + + /*frame header qp information*/ + unsigned char base_qindex; // the maximum qp is 255 + char y_dc_delta_q; + char u_dc_delta_q; + char v_dc_delta_q; + char u_ac_delta_q; + char v_ac_delta_q; + unsigned char qm_y; // 4bit: 0-15 + unsigned char qm_u; + unsigned char qm_v; + + /*cdef, need to update in the new spec*/ + unsigned int cdef_y_pri_strength; // 4bit for one, max is 8 + unsigned int cdef_uv_pri_strength; // 4bit for one, max is 8 + unsigned int cdef_y_sec_strength : 16; // 2bit for one, max is 8 + unsigned int cdef_uv_sec_strength : 16; // 2bit for one, max is 8 + + /*segmentation*/ + unsigned char segment_enabled; + unsigned char segment_update_map; + unsigned char reserved7; + unsigned char segment_temporal_update; + short segment_feature_data[8][8]; + unsigned char last_active_segid; // The highest numbered segment id that has some enabled feature. + unsigned char segid_preskip; // Whether the segment id will be read before the skip syntax element. + // 1: the segment id will be read first. + // 0: the skip syntax element will be read first. + unsigned char prevsegid_flag; // 1 : previous segment id is available + unsigned char segment_quant_sign : 8; // sign bit for segment alternative QP + + /*loopfilter*/ + unsigned char filter_level[2]; + unsigned char filter_level_u; + unsigned char filter_level_v; + unsigned char lf_sharpness_level; + char lf_ref_deltas[8]; // 0 = Intra, Last, Last2+Last3, GF, BRF, ARF2, ARF + char lf_mode_deltas[2]; // 0 = ZERO_MV, MV + + /*restoration*/ + unsigned char lr_type ; // restoration type. Y:bit[1:0];U:bit[3:2],V:bit[5:4] + unsigned char lr_unit_size; // restoration unit size 0:32x32, 1:64x64, 2:128x128,3:256x256; Y:bit[1:0];U:bit[3:2],V:bit[5:4] + + //general + frame_info_t current_frame; + ref_frame_struct_s ref_frame[7]; // Last, Last2, Last3, Golden, BWDREF, ALTREF2, ALTREF + + unsigned int use_temporal0_mvs : 1; + unsigned int use_temporal1_mvs : 1; + unsigned int use_temporal2_mvs : 1; + unsigned int mf1_type : 3; + unsigned int mf2_type : 3; + unsigned int mf3_type : 3; + unsigned int reserved_mfmv : 20; + + short mfmv_offset[3][7]; // 3: mf0~2, 7: Last, Last2, Last3, Golden, BWDREF, ALTREF2, ALTREF + char mfmv_side[3][7]; // flag for reverse offset great than 0 + // MFMV relative offset from the ref frame(reference to reference relative offset) + + unsigned char tileformat : 2; // 0: TBL; 1: KBL; + unsigned char gob_height : 3; // Set GOB height, 0: GOB_2, 1: GOB_4, 2: GOB_8, 3: GOB_16, 4: GOB_32 (NVDEC3 onwards) + unsigned char errorConcealOn : 1; // this field is not used, use ctrl_param.error_conceal_on to enable error concealment in ucode, + // always set NV_CNVDEC_GIP_ERR_CONCEAL_CTRL_ON = 1 to enable error detect in hw + unsigned char reserver8 : 2; // reserve + + unsigned char stream_error_detection : 1; + unsigned char mv_error_detection : 1; + unsigned char coeff_error_detection : 1; + unsigned char reserved_eh : 5; + + // Filt neighbor buffer offset + unsigned int Av1FltTopOffset; // filter top buffer offset respect to filter buffer, 256 bytes unit + unsigned int Av1FltVertOffset; // filter vertical buffer offset respect to filter buffer, 256 bytes unit + unsigned int Av1CdefVertOffset; // cdef vertical buffer offset respect to filter buffer, 256 bytes unit + unsigned int Av1LrVertOffset; // lr vertical buffer offset respect to filter buffer, 256 bytes unit + unsigned int Av1HusVertOffset; // hus vertical buffer offset respect to filter buffer, 256 bytes unit + unsigned int Av1FgsVertOffset; // fgs vertical buffer offset respect to filter buffer, 256 bytes unit + + unsigned int enable_histogram : 1; + unsigned int sw_skip_start_length : 14; //skip start length + unsigned int reserved_stat : 17; + +} nvdec_av1_pic_s; + +////////////////////////////////////////////////////////////////////// +// AV1 Buffer structure +////////////////////////////////////////////////////////////////////// +typedef struct _AV1FilmGrainMemory + { + unsigned char scaling_lut_y[256]; + unsigned char scaling_lut_cb[256]; + unsigned char scaling_lut_cr[256]; + short cropped_luma_grain_block[4096]; + short cropped_cb_grain_block[1024]; + short cropped_cr_grain_block[1024]; +} AV1FilmGrainMemory; + +typedef struct _AV1TileInfo_OLD +{ + unsigned char width_in_sb; + unsigned char height_in_sb; + unsigned char tile_start_b0; + unsigned char tile_start_b1; + unsigned char tile_start_b2; + unsigned char tile_start_b3; + unsigned char tile_end_b0; + unsigned char tile_end_b1; + unsigned char tile_end_b2; + unsigned char tile_end_b3; + unsigned char padding[6]; +} AV1TileInfo_OLD; + +typedef struct _AV1TileInfo +{ + unsigned char width_in_sb; + unsigned char padding_w; + unsigned char height_in_sb; + unsigned char padding_h; +} AV1TileInfo; + +typedef struct _AV1TileStreamInfo +{ + unsigned int tile_start; + unsigned int tile_end; + unsigned char padding[8]; +} AV1TileStreamInfo; + + +// AV1 TileSize buffer +#define AV1_MAX_TILES 256 +#define AV1_TILEINFO_BUF_SIZE_OLD NVDEC_ALIGN(AV1_MAX_TILES * sizeof(AV1TileInfo_OLD)) +#define AV1_TILEINFO_BUF_SIZE NVDEC_ALIGN(AV1_MAX_TILES * sizeof(AV1TileInfo)) + +// AV1 TileStreamInfo buffer +#define AV1_TILESTREAMINFO_BUF_SIZE NVDEC_ALIGN(AV1_MAX_TILES * sizeof(AV1TileStreamInfo)) + +// AV1 SubStreamEntry buffer +#define MAX_SUBSTREAM_ENTRY_SIZE 32 +#define AV1_SUBSTREAM_ENTRY_BUF_SIZE NVDEC_ALIGN(MAX_SUBSTREAM_ENTRY_SIZE * sizeof(nvdec_substream_entry_s)) + +// AV1 FilmGrain Parameter buffer +#define AV1_FGS_BUF_SIZE NVDEC_ALIGN(sizeof(AV1FilmGrainMemory)) + +// AV1 Temporal MV buffer +#define AV1_TEMPORAL_MV_SIZE_IN_64x64 256 // 4Bytes for 8x8 +#define AV1_TEMPORAL_MV_BUF_SIZE(w, h) ALIGN_UP( ALIGN_UP(w,128) * ALIGN_UP(h,128) / (64*64) * AV1_TEMPORAL_MV_SIZE_IN_64x64, 4096) + +// AV1 SegmentID buffer +#define AV1_SEGMENT_ID_SIZE_IN_64x64 128 // (3bits + 1 pad_bits) for 4x4 +#define AV1_SEGMENT_ID_BUF_SIZE(w, h) ALIGN_UP( ALIGN_UP(w,128) * ALIGN_UP(h,128) / (64*64) * AV1_SEGMENT_ID_SIZE_IN_64x64, 4096) + +// AV1 Global Motion buffer +#define AV1_GLOBAL_MOTION_BUF_SIZE NVDEC_ALIGN(7*32) + +// AV1 Intra Top buffer +#define AV1_INTRA_TOP_BUF_SIZE NVDEC_ALIGN(8*8192) + +// AV1 Histogram buffer +#define AV1_HISTOGRAM_BUF_SIZE NVDEC_ALIGN(1024) + +// AV1 Filter FG buffer +#define AV1_DBLK_TOP_SIZE_IN_SB64 ALIGN_UP(1920, 128) +#define AV1_DBLK_TOP_BUF_SIZE(w) NVDEC_ALIGN( (ALIGN_UP(w,64)/64 + 2) * AV1_DBLK_TOP_SIZE_IN_SB64) + +#define AV1_DBLK_LEFT_SIZE_IN_SB64 ALIGN_UP(1536, 128) +#define AV1_DBLK_LEFT_BUF_SIZE(h) NVDEC_ALIGN( (ALIGN_UP(h,64)/64 + 2) * AV1_DBLK_LEFT_SIZE_IN_SB64) + +#define AV1_CDEF_LEFT_SIZE_IN_SB64 ALIGN_UP(1792, 128) +#define AV1_CDEF_LEFT_BUF_SIZE(h) NVDEC_ALIGN( (ALIGN_UP(h,64)/64 + 2) * AV1_CDEF_LEFT_SIZE_IN_SB64) + +#define AV1_HUS_LEFT_SIZE_IN_SB64 ALIGN_UP(12544, 128) +#define AV1_ASIC_HUS_LEFT_BUFFER_SIZE(h) NVDEC_ALIGN( (ALIGN_UP(h,64)/64 + 2) * AV1_HUS_LEFT_SIZE_IN_SB64) +#define AV1_HUS_LEFT_BUF_SIZE(h) 2*AV1_ASIC_HUS_LEFT_BUFFER_SIZE(h) // Ping-Pong buffers + +#define AV1_LR_LEFT_SIZE_IN_SB64 ALIGN_UP(1920, 128) +#define AV1_LR_LEFT_BUF_SIZE(h) NVDEC_ALIGN( (ALIGN_UP(h,64)/64 + 2) * AV1_LR_LEFT_SIZE_IN_SB64) + +#define AV1_FGS_LEFT_SIZE_IN_SB64 ALIGN_UP(320, 128) +#define AV1_FGS_LEFT_BUF_SIZE(h) NVDEC_ALIGN( (ALIGN_UP(h,64)/64 + 2) * AV1_FGS_LEFT_SIZE_IN_SB64) + +// AV1 Hint Dump Buffer +#define AV1_HINT_DUMP_SIZE_IN_SB64 ((64*64)/(4*4)*8) // 8 bytes per CU, 256 CUs(2048 bytes) per SB64 +#define AV1_HINT_DUMP_SIZE_IN_SB128 ((128*128)/(4*4)*8) // 8 bytes per CU,1024 CUs(8192 bytes) per SB128 +#define AV1_HINT_DUMP_SIZE(w, h) NVDEC_ALIGN(AV1_HINT_DUMP_SIZE_IN_SB128*((w+127)/128)*((h+127)/128)) // always use SB128 for allocation + + +/******************************************************************* + New H264 +********************************************************************/ +typedef struct _nvdec_new_h264_pic_s +{ + nvdec_pass2_otf_s encryption_params; + unsigned char eos[16]; + unsigned char explicitEOSPresentFlag; + unsigned char hint_dump_en; //enable COLOMV surface dump for all frames, which includes hints of "MV/REFIDX/QP/CBP/MBPART/MBTYPE", nvbug: 200212874 + unsigned char reserved0[2]; + unsigned int stream_len; + unsigned int slice_count; + unsigned int mbhist_buffer_size; // to pass buffer size of MBHIST_BUFFER + + // Driver may or may not use based upon need. + // If 0 then default value of 1<<27 = 298ms @ 450MHz will be used in ucode. + // Driver can send this value based upon resolution using the formula: + // gptimer_timeout_value = 3 * (cycles required for one frame) + unsigned int gptimer_timeout_value; + + // Fields from msvld_h264_seq_s + int log2_max_pic_order_cnt_lsb_minus4; + int delta_pic_order_always_zero_flag; + int frame_mbs_only_flag; + int PicWidthInMbs; + int FrameHeightInMbs; + + unsigned int tileFormat : 2 ; // 0: TBL; 1: KBL; 2: Tile16x16 + unsigned int gob_height : 3 ; // Set GOB height, 0: GOB_2, 1: GOB_4, 2: GOB_8, 3: GOB_16, 4: GOB_32 (NVDEC3 onwards) + unsigned int reserverd_surface_format : 27; + + // Fields from msvld_h264_pic_s + int entropy_coding_mode_flag; + int pic_order_present_flag; + int num_ref_idx_l0_active_minus1; + int num_ref_idx_l1_active_minus1; + int deblocking_filter_control_present_flag; + int redundant_pic_cnt_present_flag; + int transform_8x8_mode_flag; + + // Fields from mspdec_h264_picture_setup_s + unsigned int pitch_luma; // Luma pitch + unsigned int pitch_chroma; // chroma pitch + + unsigned int luma_top_offset; // offset of luma top field in units of 256 + unsigned int luma_bot_offset; // offset of luma bottom field in units of 256 + unsigned int luma_frame_offset; // offset of luma frame in units of 256 + unsigned int chroma_top_offset; // offset of chroma top field in units of 256 + unsigned int chroma_bot_offset; // offset of chroma bottom field in units of 256 + unsigned int chroma_frame_offset; // offset of chroma frame in units of 256 + unsigned int HistBufferSize; // in units of 256 + + unsigned int MbaffFrameFlag : 1; // + unsigned int direct_8x8_inference_flag: 1; // + unsigned int weighted_pred_flag : 1; // + unsigned int constrained_intra_pred_flag:1; // + unsigned int ref_pic_flag : 1; // reference picture (nal_ref_idc != 0) + unsigned int field_pic_flag : 1; // + unsigned int bottom_field_flag : 1; // + unsigned int second_field : 1; // second field of complementary reference field + unsigned int log2_max_frame_num_minus4: 4; // (0..12) + unsigned int chroma_format_idc : 2; // + unsigned int pic_order_cnt_type : 2; // (0..2) + int pic_init_qp_minus26 : 6; // : 6 (-26..+25) + int chroma_qp_index_offset : 5; // : 5 (-12..+12) + int second_chroma_qp_index_offset : 5; // : 5 (-12..+12) + + unsigned int weighted_bipred_idc : 2; // : 2 (0..2) + unsigned int CurrPicIdx : 7; // : 7 uncompressed frame buffer index + unsigned int CurrColIdx : 5; // : 5 index of associated co-located motion data buffer + unsigned int frame_num : 16; // + unsigned int frame_surfaces : 1; // frame surfaces flag + unsigned int output_memory_layout : 1; // 0: NV12; 1:NV24. Field pair must use the same setting. + + int CurrFieldOrderCnt[2]; // : 32 [Top_Bottom], [0]=TopFieldOrderCnt, [1]=BottomFieldOrderCnt + nvdec_dpb_entry_s dpb[16]; + unsigned char WeightScale[6][4][4]; // : 6*4*4*8 in raster scan order (not zig-zag order) + unsigned char WeightScale8x8[2][8][8]; // : 2*8*8*8 in raster scan order (not zig-zag order) + + // mvc setup info, must be zero if not mvc + unsigned char num_inter_view_refs_lX[2]; // number of inter-view references + char reserved1[14]; // reserved for alignment + signed char inter_view_refidx_lX[2][16]; // DPB indices (must also be marked as long-term) + + // lossless decode (At the time of writing this manual, x264 and JM encoders, differ in Intra_8x8 reference sample filtering) + unsigned int lossless_ipred8x8_filter_enable : 1; // = 0, skips Intra_8x8 reference sample filtering, for vertical and horizontal predictions (x264 encoded streams); = 1, filter Intra_8x8 reference samples (JM encoded streams) + unsigned int qpprime_y_zero_transform_bypass_flag : 1; // determines the transform bypass mode + unsigned int reserved2 : 30; // kept for alignment; may be used for other parameters + + nvdec_display_param_s displayPara; + nvdec_pass2_otf_ext_s ssm; + +} nvdec_new_h264_pic_s; + +// golden crc struct dumped into surface +// for each part, if golden crc compare is enabled, one interface is selected to do crc calculation in vmod. +// vmod's crc is compared with cmod's golden crc (4*32 bits), and compare reuslt is written into surface. +typedef struct +{ + // input + unsigned int dbg_crc_enable_partb : 1; // Eable flag for enable/disable interface crc calculation in NVDEC HW's part b + unsigned int dbg_crc_enable_partc : 1; // Eable flag for enable/disable interface crc calculation in NVDEC HW's part c + unsigned int dbg_crc_enable_partd : 1; // Eable flag for enable/disable interface crc calculation in NVDEC HW's part d + unsigned int dbg_crc_enable_parte : 1; // Eable flag for enable/disable interface crc calculation in NVDEC HW's part e + unsigned int dbg_crc_intf_partb : 6; // For partb to select which interface to compare crc. see DBG_CRC_PARTE_INTF_SEL for detailed control value for each interface + unsigned int dbg_crc_intf_partc : 6; // For partc to select which interface to compare crc. see DBG_CRC_PARTE_INTF_SEL for detailed control value for each interface + unsigned int dbg_crc_intf_partd : 6; // For partd to select which interface to compare crc. see DBG_CRC_PARTE_INTF_SEL for detailed control value for each interface + unsigned int dbg_crc_intf_parte : 6; // For parte to select which interface to compare crc. see DBG_CRC_PARTE_INTF_SEL for detailed control value for each interface + unsigned int reserved0 : 4; + + unsigned int dbg_crc_partb_golden[4]; // Golden crc values for part b + unsigned int dbg_crc_partc_golden[4]; // Golden crc values for part c + unsigned int dbg_crc_partd_golden[4]; // Golden crc values for part d + unsigned int dbg_crc_parte_golden[4]; // Golden crc values for part e + + // output + unsigned int dbg_crc_comp_partb : 4; // Compare result for part b + unsigned int dbg_crc_comp_partc : 4; // Compare result for part c + unsigned int dbg_crc_comp_partd : 4; // Compare result for part d + unsigned int dbg_crc_comp_parte : 4; // Compare result for part e + unsigned int reserved1 : 16; + + unsigned char reserved2[56]; +}nvdec_crc_s; // 128 Bytes + +#endif /* AVUTIL_DRV_NVDEC_H */ diff --git a/libavutil/nvjpg_drv.h b/libavutil/nvjpg_drv.h new file mode 100644 index 0000000000..cd8e976952 --- /dev/null +++ b/libavutil/nvjpg_drv.h @@ -0,0 +1,189 @@ +/******************************************************************************* + Copyright (c) 2016-2020, NVIDIA CORPORATION. All rights reserved. + + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + +*******************************************************************************/ + +#ifndef AVUTIL_NVJPG_DRV_H +#define AVUTIL_NVJPG_DRV_H + +#include <stdint.h> + +typedef uint8_t NvU8; +typedef uint16_t NvU16; +typedef uint32_t NvU32; +typedef uint64_t NvU64; +typedef int8_t NvS8; +typedef int16_t NvS16; +typedef int32_t NvS32; +typedef int64_t NvS64; +typedef _Bool NvBool; + +// +// CLASS NV_E7D0_NVJPG +// +// NVJPG is the combination of JPEG decoder and encoder, it will support baseline sequential profile. +// In the encoder side, it support: a. 420 pitch linear format, b. programable huffman/qunat table, ... etc. +// In the decoder side, it support: a. 400/420/422/444 decoding, b. YUV2RGB, c. Power2Scale: 1/2, 1/4, 1/8, d.ChromaSumbSample ... etc. +// =================== + + +// huffuman table: +// huffuman table is organized in symbol value order, each table item include 2 field, codeWord length, and codeWord value +#define DCVALUEITEM 12 +#define ACVALUEITEM 256 // in fact, only 162 items are used in baseline sequential profile. +typedef struct +{ + unsigned short length; // 4 bit, code word length + unsigned short value; // 16 bit, code word value +}huffman_symbol_s; + + +typedef struct +{ + // surface related + unsigned int bitstream_start_off;// start offset position in bitstream buffer where data should be written (byte offset) + unsigned int bitstream_buf_size; // size in bytes of the buffer allocated for bitstream slice/mb data + unsigned int luma_stride; // 64 bytes align; + unsigned int chroma_stride; // 64 bytes align; + unsigned int inputType : 4; // 0: YUV; 1: RGB, 2: BGR, 3:RGBA, 4: BGRA, 5: ABGR, 6: ARGB + unsigned int chromaFormat : 2; // chroma format: 0: 444; 1: 422H; 2:422V; 3:420 + unsigned int tilingMode : 2; // 0: linear; 1: GPU_blkLinear; 2: Tegra_blkLinear + unsigned int gobHeight : 3; // used for blkLinear, 0: 2; 1: 4; ... 4: 32 + unsigned int yuvMemoryMode: 3; // 0-semi planar nv12; 1-semi planar nv21; 2-plane(yuy2); 3-planar + unsigned int reserved_0 : 18; + // control para + unsigned short imageWidth; // real image width, up to 16K + unsigned short imageHeight; // real image height, up to 16K + unsigned short jpegWidth; // image width align to 8 or 16 pixel + unsigned short jpegHeight; // image height align to 8 or 16 pixel + unsigned int totalMcu; + unsigned int widthMcu; + unsigned int heightMcu; + unsigned int restartInterval; // restart interval, 0 means disable the restart feature + + // rate control related + unsigned int rateControl : 2; // RC: 0:disable; 1:block-base; others: reserve + unsigned int rcTargetYBits : 11; // target luma bits per block, [0 ~ (1<<11)-1] + unsigned int rcTargetCBits : 11; // target chroma bits per block, [0 ~ (1<<11)-1] + unsigned int reserved_1 : 8; + unsigned int preQuant : 1; // pre quant trunction enabled flag + unsigned int rcThreshIdx : 8; // pre_quant threshold index [1 ~ 63] + unsigned int rcThreshMag : 21; // threshold magnitude + // mjpeg-typeB + unsigned int isMjpgTypeB : 1; // a flag indicate mjpg type B format, which control HW no stuff byte. + unsigned int reserved_2 : 1; + // huffman tables + huffman_symbol_s hfDcLuma[DCVALUEITEM]; //dc luma huffman table, arranged in symbol increase order, encoder can directly index and use + huffman_symbol_s hfAcLuma[ACVALUEITEM]; //ac luma huffman table, arranged in symbol increase order, encoder can directly index and use + huffman_symbol_s hfDcChroma[DCVALUEITEM]; //dc chroma huffman table, arranged in symbol increase order, encoder can directly index and use + huffman_symbol_s hfAcChroma[ACVALUEITEM]; //ac chroma huffman table, arranged in symbol increase order, encoder can directly index and use + // quantization tables + unsigned short quantLumaFactor[64]; //luma quantize factor table, arranged in horizontal scan order, (1<<15)/quantLuma + unsigned short quantChromaFactor[64]; //chroma quantize factor table, arranged in horizontal scan order, (1<<15)/quantLuma + + unsigned char reserve[0x6c]; +}nvjpg_enc_drv_pic_setup_s; + +typedef struct +{ + unsigned int bitstream_size; //exact residual part bitstram size of current image + unsigned int mcu_x; //encoded mcu_x + unsigned int mcu_y; //encoded mcu_y + unsigned int cycle_count; + unsigned int error_status; //report error if any + unsigned char reserved1[12]; +}nvjpg_enc_status; + +struct ctrl_param_s +{ + union + { + struct + { + unsigned int gptimer_on :1; + unsigned int dump_cycle :1; + unsigned int debug_mode :1; + unsigned int reserved :29; + }bits; + unsigned int data; + }; +}; + + +//NVJPG Decoder class interface +typedef struct +{ + int codeNum[16]; //the number of huffman code with length i + unsigned char minCodeIdx[16]; //the index of the min huffman code with length i + int minCode[16]; //the min huffman code with length i + unsigned char symbol[162]; // symbol need to be coded. + unsigned char reserved[2]; // alignment +}huffman_tab_s; + +typedef struct +{ + unsigned char hblock; + unsigned char vblock; + unsigned char quant; + unsigned char ac; + unsigned char dc; + unsigned char reserved[3]; //alignment +} block_parameter_s; + +typedef struct +{ + huffman_tab_s huffTab[2][4]; + block_parameter_s blkPar[4]; + unsigned char quant[4][64]; //quant table + int restart_interval; + int frame_width; + int frame_height; + int mcu_width; + int mcu_height; + int comp; + int bitstream_offset; + int bitstream_size; + int stream_chroma_mode; //0-mono chrome; 1-yuv420; 2-yuv422H; 3-yuv422V; 4-yuv444; + int output_chroma_mode; //0-mono chrome; 1-yuv420; 2-yuv422H; 3-yuv422V; 4-yuv444; + int output_pixel_format; //0-yuv; 1-RGB; 2-BGR; 3-RGBA; 4-BGRA; 5-ABGR; 6-ARGB + int output_stride_luma; //64 bytes align + int output_stride_chroma; //64 bytes align + int alpha_value; + int yuv2rgb_param[6]; //K0, K1, K2, K3, K4, C + int tile_mode; //0-pitch linear; 1-gpu block linear; 2-tegra block linear + int block_linear_height; + int memory_mode; //0-semi planar nv12; 1-semi planar nv21; 2-plane(yuy2); 3-planar + int power2_downscale; //0-no scale; 1- 1/2; 2- 1/4; 3- 1/8 + int motion_jpeg_type; //0-type A; 1-type B + int start_mcu_x; //set start mcu x for error robust + int start_mcu_y; //set start mcu y for error robust +}nvjpg_dec_drv_pic_setup_s; + +typedef struct +{ + unsigned int bytes_offset; //bytes consumed by HW + unsigned int mcu_x; //decoded mcu_x + unsigned int mcu_y; //decoded mcu_y + unsigned int cycle_count; + unsigned int error_status; //report error if any + unsigned char reserved1[12]; +}nvjpg_dec_status; +#endif /* AVUTIL_NVJPG_DRV_H */ diff --git a/libavutil/vic_drv.h b/libavutil/vic_drv.h new file mode 100644 index 0000000000..32ebe1a17d --- /dev/null +++ b/libavutil/vic_drv.h @@ -0,0 +1,279 @@ +/* + * Copyright (c) 2024 averne <averne381@gmail.com> + * + * This file is part of FFmpeg. + * + * FFmpeg is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * FFmpeg is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with FFmpeg; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef AVUTIL_VIC_DRV_H +#define AVUTIL_VIC_DRV_H + +#include <stdint.h> + +typedef uint8_t NvU8; +typedef uint16_t NvU16; +typedef uint32_t NvU32; +typedef uint64_t NvU64; +typedef int8_t NvS8; +typedef int16_t NvS16; +typedef int32_t NvS32; +typedef int64_t NvS64; +typedef _Bool NvBool; + +typedef struct VicPipeConfig { + NvU32 DownsampleHoriz : 11; + NvU32 reserved0 : 5; + NvU32 DownsampleVert : 11; + NvU32 reserved1 : 5; + NvU32 reserved2 : 32; + NvU32 reserved3 : 32; + NvU32 reserved4 : 32; +} VicPipeConfig; + +typedef struct VicOutputConfig { + NvU64 AlphaFillMode : 3; + NvU64 AlphaFillSlot : 3; + NvU64 BackgroundAlpha : 10; + NvU64 BackgroundR : 10; + NvU64 BackgroundG : 10; + NvU64 BackgroundB : 10; + NvU64 RegammaMode : 2; + NvU64 OutputFlipX : 1; + NvU64 OutputFlipY : 1; + NvU64 OutputTranspose : 1; + NvU64 reserved1 : 1; + NvU64 reserved2 : 12; + NvU32 TargetRectLeft : 14; + NvU32 reserved3 : 2; + NvU32 TargetRectRight : 14; + NvU32 reserved4 : 2; + NvU32 TargetRectTop : 14; + NvU32 reserved5 : 2; + NvU32 TargetRectBottom : 14; + NvU32 reserved6 : 2; +} VicOutputConfig; + +typedef struct VicOutputSurfaceConfig { + NvU32 OutPixelFormat : 7; + NvU32 OutChromaLocHoriz : 2; + NvU32 OutChromaLocVert : 2; + NvU32 OutBlkKind : 4; + NvU32 OutBlkHeight : 4; + NvU32 reserved0 : 3; + NvU32 reserved1 : 10; + NvU32 OutSurfaceWidth : 14; + NvU32 OutSurfaceHeight : 14; + NvU32 reserved2 : 4; + NvU32 OutLumaWidth : 14; + NvU32 OutLumaHeight : 14; + NvU32 reserved3 : 4; + NvU32 OutChromaWidth : 14; + NvU32 OutChromaHeight : 14; + NvU32 reserved4 : 4; +} VicOutputSurfaceConfig; + +typedef struct VicMatrixStruct { + NvU64 matrix_coeff00 : 20; + NvU64 matrix_coeff10 : 20; + NvU64 matrix_coeff20 : 20; + NvU64 matrix_r_shift : 4; + NvU64 matrix_coeff01 : 20; + NvU64 matrix_coeff11 : 20; + NvU64 matrix_coeff21 : 20; + NvU64 reserved0 : 3; + NvU64 matrix_enable : 1; + NvU64 matrix_coeff02 : 20; + NvU64 matrix_coeff12 : 20; + NvU64 matrix_coeff22 : 20; + NvU64 reserved1 : 4; + NvU64 matrix_coeff03 : 20; + NvU64 matrix_coeff13 : 20; + NvU64 matrix_coeff23 : 20; + NvU64 reserved2 : 4; +} VicMatrixStruct; + +typedef struct VicClearRectStruct { + NvU32 ClearRect0Left : 14; + NvU32 reserved0 : 2; + NvU32 ClearRect0Right : 14; + NvU32 reserved1 : 2; + NvU32 ClearRect0Top : 14; + NvU32 reserved2 : 2; + NvU32 ClearRect0Bottom : 14; + NvU32 reserved3 : 2; + NvU32 ClearRect1Left : 14; + NvU32 reserved4 : 2; + NvU32 ClearRect1Right : 14; + NvU32 reserved5 : 2; + NvU32 ClearRect1Top : 14; + NvU32 reserved6 : 2; + NvU32 ClearRect1Bottom : 14; + NvU32 reserved7 : 2; +} VicClearRectStruct; + +typedef struct VicSlotStructSlotConfig { + NvU64 SlotEnable : 1; + NvU64 DeNoise : 1; + NvU64 AdvancedDenoise : 1; + NvU64 CadenceDetect : 1; + NvU64 MotionMap : 1; + NvU64 MMapCombine : 1; + NvU64 IsEven : 1; + NvU64 ChromaEven : 1; + NvU64 CurrentFieldEnable : 1; + NvU64 PrevFieldEnable : 1; + NvU64 NextFieldEnable : 1; + NvU64 NextNrFieldEnable : 1; + NvU64 CurMotionFieldEnable : 1; + NvU64 PrevMotionFieldEnable : 1; + NvU64 PpMotionFieldEnable : 1; + NvU64 CombMotionFieldEnable : 1; + NvU64 FrameFormat : 4; + NvU64 FilterLengthY : 2; + NvU64 FilterLengthX : 2; + NvU64 Panoramic : 12; + NvU64 reserved1 : 22; + NvU64 DetailFltClamp : 6; + NvU64 FilterNoise : 10; + NvU64 FilterDetail : 10; + NvU64 ChromaNoise : 10; + NvU64 ChromaDetail : 10; + NvU64 DeinterlaceMode : 4; + NvU64 MotionAccumWeight : 3; + NvU64 NoiseIir : 11; + NvU64 LightLevel : 4; + NvU64 reserved4 : 2; + NvU32 SoftClampLow : 10; + NvU32 SoftClampHigh : 10; + NvU32 reserved5 : 3; + NvU32 reserved6 : 9; + NvU32 PlanarAlpha : 10; + NvU32 ConstantAlpha : 1; + NvU32 StereoInterleave : 3; + NvU32 ClipEnabled : 1; + NvU32 ClearRectMask : 8; + NvU32 DegammaMode : 2; + NvU32 reserved7 : 1; + NvU32 DecompressEnable : 1; + NvU32 reserved9 : 5; + NvU64 DecompressCtbCount : 8; + NvU64 DecompressZbcColor : 32; + NvU64 reserved12 : 24; + NvU32 SourceRectLeft : 30; + NvU32 reserved14 : 2; + NvU32 SourceRectRight : 30; + NvU32 reserved15 : 2; + NvU32 SourceRectTop : 30; + NvU32 reserved16 : 2; + NvU32 SourceRectBottom : 30; + NvU32 reserved17 : 2; + NvU32 DestRectLeft : 14; + NvU32 reserved18 : 2; + NvU32 DestRectRight : 14; + NvU32 reserved19 : 2; + NvU32 DestRectTop : 14; + NvU32 reserved20 : 2; + NvU32 DestRectBottom : 14; + NvU32 reserved21 : 2; + NvU32 reserved22 : 32; + NvU32 reserved23 : 32; +} VicSlotStructSlotConfig; + +typedef struct VicSlotStructSlotSurfaceConfig { + NvU32 SlotPixelFormat : 7; + NvU32 SlotChromaLocHoriz : 2; + NvU32 SlotChromaLocVert : 2; + NvU32 SlotBlkKind : 4; + NvU32 SlotBlkHeight : 4; + NvU32 SlotCacheWidth : 3; + NvU32 reserved0 : 10; + NvU32 SlotSurfaceWidth : 14; + NvU32 SlotSurfaceHeight : 14; + NvU32 reserved1 : 4; + NvU32 SlotLumaWidth : 14; + NvU32 SlotLumaHeight : 14; + NvU32 reserved2 : 4; + NvU32 SlotChromaWidth : 14; + NvU32 SlotChromaHeight : 14; + NvU32 reserved3 : 4; +} VicSlotStructSlotSurfaceConfig; + +typedef struct VicSlotStructLumaKeyStruct { + NvU64 luma_coeff0 : 20; + NvU64 luma_coeff1 : 20; + NvU64 luma_coeff2 : 20; + NvU64 luma_r_shift : 4; + NvU64 luma_coeff3 : 20; + NvU64 LumaKeyLower : 10; + NvU64 LumaKeyUpper : 10; + NvU64 LumaKeyEnabled : 1; + NvU64 reserved0 : 2; + NvU64 reserved1 : 21; +} VicSlotStructLumaKeyStruct; + +typedef struct VicSlotStructBlendingSlotStruct { + NvU32 AlphaK1 : 10; + NvU32 reserved0 : 6; + NvU32 AlphaK2 : 10; + NvU32 reserved1 : 6; + NvU32 SrcFactCMatchSelect : 3; + NvU32 reserved2 : 1; + NvU32 DstFactCMatchSelect : 3; + NvU32 reserved3 : 1; + NvU32 SrcFactAMatchSelect : 3; + NvU32 reserved4 : 1; + NvU32 DstFactAMatchSelect : 3; + NvU32 reserved5 : 1; + NvU32 reserved6 : 4; + NvU32 reserved7 : 4; + NvU32 reserved8 : 4; + NvU32 reserved9 : 4; + NvU32 reserved10 : 2; + NvU32 OverrideR : 10; + NvU32 OverrideG : 10; + NvU32 OverrideB : 10; + NvU32 OverrideA : 10; + NvU32 reserved11 : 2; + NvU32 UseOverrideR : 1; + NvU32 UseOverrideG : 1; + NvU32 UseOverrideB : 1; + NvU32 UseOverrideA : 1; + NvU32 MaskR : 1; + NvU32 MaskG : 1; + NvU32 MaskB : 1; + NvU32 MaskA : 1; + NvU32 reserved12 : 12; +} VicSlotStructBlendingSlotStruct; + +typedef struct VicSlotStruct { + VicSlotStructSlotConfig slotConfig; + VicSlotStructSlotSurfaceConfig slotSurfaceConfig; + VicSlotStructLumaKeyStruct lumaKeyStruct; + VicMatrixStruct colorMatrixStruct; + VicMatrixStruct gamutMatrixStruct; + VicSlotStructBlendingSlotStruct blendingSlotStruct; +} VicSlotStruct; + +typedef struct VicConfigStruct { + VicPipeConfig pipeConfig; + VicOutputConfig outputConfig; + VicOutputSurfaceConfig outputSurfaceConfig; + VicMatrixStruct outColorMatrixStruct; + VicClearRectStruct clearRectStruct[4]; + VicSlotStruct slotStruct[8]; +} VicConfigStruct; + +#endif /* AVUTIL_VIC_DRV_H */

[FFmpeg-devel,04/16] avutil: add hardware definitions for NVDEC, NVJPG and VIC

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