From e1a01b1e0a365935868d7825d53c7cc64e2c1787 Mon Sep 17 00:00:00 2001
From: sunyuechi <sunyuechi@iscas.ac.cn>
Date: Fri, 23 Feb 2024 22:35:23 +0800
Subject: [PATCH 3/3] lavc/vp8dsp: R-V V put_bilin_hv
C908:
vp8_put_bilin4_hv_c: 567.7
vp8_put_bilin4_hv_rvv_i32: 255.7
vp8_put_bilin8_hv_c: 2169.5
vp8_put_bilin8_hv_rvv_i32: 528.7
vp8_put_bilin16_hv_c: 4777.5
vp8_put_bilin16_hv_rvv_i32: 587.7
---
libavcodec/riscv/vp8dsp_init.c | 13 +++++++++++++
libavcodec/riscv/vp8dsp_rvv.S | 35 ++++++++++++++++++++++++++++++++++
2 files changed, 48 insertions(+)
@@ -65,6 +65,19 @@ av_cold void ff_vp78dsp_init_riscv(VP8DSPContext *c)
c->put_vp8_bilinear_pixels_tab[1][2][0] = ff_put_vp8_bilin8_v_rvv;
c->put_vp8_bilinear_pixels_tab[2][1][0] = ff_put_vp8_bilin4_v_rvv;
c->put_vp8_bilinear_pixels_tab[2][2][0] = ff_put_vp8_bilin4_v_rvv;
+
+ c->put_vp8_bilinear_pixels_tab[0][1][1] = ff_put_vp8_bilin16_hv_rvv;
+ c->put_vp8_bilinear_pixels_tab[0][1][2] = ff_put_vp8_bilin16_hv_rvv;
+ c->put_vp8_bilinear_pixels_tab[0][2][1] = ff_put_vp8_bilin16_hv_rvv;
+ c->put_vp8_bilinear_pixels_tab[0][2][2] = ff_put_vp8_bilin16_hv_rvv;
+ c->put_vp8_bilinear_pixels_tab[1][1][1] = ff_put_vp8_bilin8_hv_rvv;
+ c->put_vp8_bilinear_pixels_tab[1][1][2] = ff_put_vp8_bilin8_hv_rvv;
+ c->put_vp8_bilinear_pixels_tab[1][2][1] = ff_put_vp8_bilin8_hv_rvv;
+ c->put_vp8_bilinear_pixels_tab[1][2][2] = ff_put_vp8_bilin8_hv_rvv;
+ c->put_vp8_bilinear_pixels_tab[2][1][1] = ff_put_vp8_bilin4_hv_rvv;
+ c->put_vp8_bilinear_pixels_tab[2][1][2] = ff_put_vp8_bilin4_hv_rvv;
+ c->put_vp8_bilinear_pixels_tab[2][2][1] = ff_put_vp8_bilin4_hv_rvv;
+ c->put_vp8_bilinear_pixels_tab[2][2][2] = ff_put_vp8_bilin4_hv_rvv;
}
#endif
}
@@ -188,3 +188,38 @@ func ff_put_vp8_bilin4_v_rvv, zve32x
vsetivli zero, 4, e8, mf4, ta, ma
put_vp8_bilin_v
endfunc
+
+.macro put_vp8_bilin_hv len
+ li t3, 8
+ sub t1, t3, a5
+ sub t2, t3, a6
+ li t4, 4
+ li t5, 1
+ bilin_h_load v4, \len
+ add a2, a2, a3
+1:
+ addi a4, a4, -1
+ vwmulu.vx v20, v4, t2
+ bilin_h_load v4, \len
+ vwmaccu.vx v20, a6, v4
+ vwaddu.wx v24, v20, t4
+ vnsra.wi v0, v24, 3
+ vse8.v v0, (a0)
+ add a2, a2, a3
+ add a0, a0, a1
+ bnez a4, 1b
+
+ ret
+.endm
+
+func ff_put_vp8_bilin16_hv_rvv, zve32x
+ put_vp8_bilin_hv 16
+endfunc
+
+func ff_put_vp8_bilin8_hv_rvv, zve32x
+ put_vp8_bilin_hv 8
+endfunc
+
+func ff_put_vp8_bilin4_hv_rvv, zve32x
+ put_vp8_bilin_hv 4
+endfunc
--
2.43.2