| Message ID | CAEa-L+uQ7ROWr_Bri=H6zXs6mW1Tkejc32U0zvnGCTrp7jaX3g@mail.gmail.com |
|---|---|
| State | New |
| Headers | show |
| Series | [FFmpeg-devel] lavc/vc1dsp: R-V V inv_trans | expand |
| Context | Check | Description |
|---|---|---|
| andriy/make_x86 | success | Make finished |
| andriy/make_fate_x86 | success | Make fate finished |
Le sunnuntaina 3. joulukuuta 2023, 16.40.08 EET flow gg a écrit : > c910 > vc1dsp.vc1_inv_trans_4x4_dc_c: 84.0 > vc1dsp.vc1_inv_trans_4x4_dc_rvv_i32: 74.0 > vc1dsp.vc1_inv_trans_4x8_dc_c: 150.2 > vc1dsp.vc1_inv_trans_4x8_dc_rvv_i32: 83.5 > vc1dsp.vc1_inv_trans_8x4_dc_c: 129.0 > vc1dsp.vc1_inv_trans_8x4_dc_rvv_i64: 75.7 > vc1dsp.vc1_inv_trans_8x8_dc_c: 254.7 > vc1dsp.vc1_inv_trans_8x8_dc_rvv_i64: 90.5 The code below uses fractional multipliers, so I infer that the benchmarked code was significantly different, and the measurements are not really worth the bother. I know that supply is a problem at the moment, but I if you are going to keep this up, I would hope that ISCAS can get you access to an RVV 1.0 board. In-line... > diff --git a/libavcodec/riscv/vc1dsp_init.c b/libavcodec/riscv/vc1dsp_init.c > new file mode 100644 > index 0000000000..88e0434f0e > --- /dev/null > +++ b/libavcodec/riscv/vc1dsp_init.c > @@ -0,0 +1,47 @@ > +/* > + * Copyright (c) 2023 Institue of Software Chinese Academy of Sciences > (ISCAS). > + * > + * This file is part of FFmpeg. > + * > + * FFmpeg is free software; you can redistribute it and/or > + * modify it under the terms of the GNU Lesser General Public > + * License as published by the Free Software Foundation; either > + * version 2.1 of the License, or (at your option) any later version. > + * > + * FFmpeg is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU > + * Lesser General Public License for more details. > + * > + * You should have received a copy of the GNU Lesser General Public > + * License along with FFmpeg; if not, write to the Free Software > + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 > USA > + */ > + > +#include <stdint.h> > + > +#include "libavutil/attributes.h" > +#include "libavutil/cpu.h" > +#include "libavutil/riscv/cpu.h" > +#include "libavcodec/vc1.h" > + > +void ff_vc1_inv_trans_8x8_dc_rvv(uint8_t *dest, ptrdiff_t stride, int16_t > *block); > +void ff_vc1_inv_trans_4x8_dc_rvv(uint8_t *dest, ptrdiff_t stride, int16_t > *block); > +void ff_vc1_inv_trans_8x4_dc_rvv(uint8_t *dest, ptrdiff_t stride, int16_t > *block); > +void ff_vc1_inv_trans_4x4_dc_rvv(uint8_t *dest, ptrdiff_t stride, int16_t > *block); > + > +av_cold void ff_vc1dsp_init_riscv(VC1DSPContext *dsp) > +{ > +#if HAVE_RVV > + int flags = av_get_cpu_flags(); > + > + if (flags & AV_CPU_FLAG_RVV_I64) { > + dsp->vc1_inv_trans_8x8_dc = ff_vc1_inv_trans_8x8_dc_rvv; > + dsp->vc1_inv_trans_8x4_dc = ff_vc1_inv_trans_8x4_dc_rvv; > + } > + if (flags & AV_CPU_FLAG_RVV_I32) { > + dsp->vc1_inv_trans_4x8_dc = ff_vc1_inv_trans_4x8_dc_rvv; > + dsp->vc1_inv_trans_4x4_dc = ff_vc1_inv_trans_4x4_dc_rvv; > + } Probably missing VLENB checks. > +#endif > +} > diff --git a/libavcodec/riscv/vc1dsp_rvv.S b/libavcodec/riscv/vc1dsp_rvv.S > new file mode 100644 > index 0000000000..8a6b27192a > --- /dev/null > +++ b/libavcodec/riscv/vc1dsp_rvv.S > @@ -0,0 +1,123 @@ > +/* > + * Copyright (c) 2023 Institue of Software Chinese Academy of Sciences > (ISCAS). > + * > + * This file is part of FFmpeg. > + * > + * FFmpeg is free software; you can redistribute it and/or > + * modify it under the terms of the GNU Lesser General Public > + * License as published by the Free Software Foundation; either > + * version 2.1 of the License, or (at your option) any later version. > + * > + * FFmpeg is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU > + * Lesser General Public License for more details. > + * > + * You should have received a copy of the GNU Lesser General Public > + * License along with FFmpeg; if not, write to the Free Software > + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 > USA > + */ > + > +#include "libavutil/riscv/asm.S" > + > +func ff_vc1_inv_trans_8x8_dc_rvv, zve64x > + lh t2, (a2) > + li t1, 3 > + mul t2, t2, t1 You can multiply by 3, 5 or 9 with shift-and-add. By 12 with shift-and-add then shift, and by 17 with shift then add. You don't need multiplications. > + addi t2, t2, 1 > + srai t2, t2, 1 > + mul t2, t2, t1 > + addi t2, t2, 16 > + srai t2, t2, 5 > + vsetivli zero, 8, e8, mf2, ta, ma > + vlse64.v v0, (a0), a1 > + li t0, 8*8 > + vsetvli zero, t0, e16, m8, ta, ma > + vmv.v.x v8, t2 Do you really need to splat? Can't .vx or .wx be used instead? > + vsetvli zero, t0, e8, m4, ta, ma > + vwaddu.wv v8, v8, v0 > + vsetvli zero, t0, e16, m8, ta, ma > + vmax.vx v8, v8, zero > + vsetvli zero, t0, e8, m4, ta, ma > + vnclipu.wi v0, v8, 0 > + vsetivli zero, 8, e8, mf2, ta, ma > + vsse64.v v0, (a0), a1 > + ret > +endfunc > + > +func ff_vc1_inv_trans_4x8_dc_rvv, zve32x > + lh t2, (a2) > + li t1, 17 > + mul t2, t2, t1 > + addi t2, t2, 4 > + srai t2, t2, 3 > + li t1, 12 > + mul t2, t2, t1 > + addi t2, t2, 64 > + srai t2, t2, 7 > + vsetivli zero, 8, e8, mf2, ta, ma > + vlse32.v v0, (a0), a1 > + li t0, 4*8 > + vsetvli zero, t0, e16, m4, ta, ma > + vmv.v.x v4, t2 > + vsetvli zero, t0, e8, m2, ta, ma > + vwaddu.wv v4, v4, v0 > + vsetvli zero, t0, e16, m4, ta, ma > + vmax.vx v4, v4, zero > + vsetvli zero, t0, e8, m2, ta, ma > + vnclipu.wi v0, v4, 0 > + vsetivli zero, 8, e8, mf2, ta, ma > + vsse32.v v0, (a0), a1 > + ret > +endfunc > + > +func ff_vc1_inv_trans_8x4_dc_rvv, zve64x > + lh t2, (a2) > + li t1, 3 > + mul t2, t2, t1 > + addi t2, t2, 1 > + srai t2, t2, 1 > + li t1, 17 > + mul t2, t2, t1 > + addi t2, t2, 64 > + srai t2, t2, 7 > + vsetivli zero, 8, e8, mf2, ta, ma > + vlse64.v v0, (a0), a1 > + li t0, 8*4 > + vsetvli zero, t0, e16, m4, ta, ma > + vmv.v.x v4, t2 > + vsetvli zero, t0, e8, m2, ta, ma > + vwaddu.wv v4, v4, v0 > + vsetvli zero, t0, e16, m4, ta, ma > + vmax.vx v4, v4, zero > + vsetvli zero, t0, e8, m2, ta, ma > + vnclipu.wi v0, v4, 0 > + vsetivli zero, 8, e8, mf2, ta, ma > + vsse64.v v0, (a0), a1 > + ret > +endfunc > + > +func ff_vc1_inv_trans_4x4_dc_rvv, zve32x > + lh t2, (a2) > + li t1, 17 > + mul t2, t2, t1 > + addi t2, t2, 4 > + srai t2, t2, 3 > + mul t2, t2, t1 > + addi t2, t2, 64 > + srai t2, t2, 7 > + vsetivli zero, 4, e8, mf2, ta, ma > + vlse32.v v0, (a0), a1 > + li t0, 4*4 > + vsetvli zero, t0, e16, m2, ta, ma > + vmv.v.x v2, t2 > + vsetvli zero, t0, e8, m1, ta, ma > + vwaddu.wv v2, v2, v0 > + vsetvli zero, t0, e16, m2, ta, ma > + vmax.vx v2, v2, zero > + vsetvli zero, t0, e8, m1, ta, ma > + vnclipu.wi v0, v2, 0 > + vsetivli zero, 4, e8, mf2, ta, ma > + vsse32.v v0, (a0), a1 > + ret > +endfunc > diff --git a/libavcodec/vc1dsp.c b/libavcodec/vc1dsp.c > index 62c8eb21fa..2caa3c6863 100644 > --- a/libavcodec/vc1dsp.c > +++ b/libavcodec/vc1dsp.c > @@ -1039,6 +1039,8 @@ av_cold void ff_vc1dsp_init(VC1DSPContext *dsp) > ff_vc1dsp_init_arm(dsp); > #elif ARCH_PPC > ff_vc1dsp_init_ppc(dsp); > +#elif ARCH_RISCV > + ff_vc1dsp_init_riscv(dsp); > #elif ARCH_X86 > ff_vc1dsp_init_x86(dsp); > #elif ARCH_MIPS > diff --git a/libavcodec/vc1dsp.h b/libavcodec/vc1dsp.h > index 7ed1776ca7..e3b90d2b62 100644 > --- a/libavcodec/vc1dsp.h > +++ b/libavcodec/vc1dsp.h > @@ -89,6 +89,7 @@ void ff_vc1dsp_init(VC1DSPContext* c); > void ff_vc1dsp_init_aarch64(VC1DSPContext* dsp); > void ff_vc1dsp_init_arm(VC1DSPContext* dsp); > void ff_vc1dsp_init_ppc(VC1DSPContext *c); > +void ff_vc1dsp_init_riscv(VC1DSPContext *c); > void ff_vc1dsp_init_x86(VC1DSPContext* dsp); > void ff_vc1dsp_init_mips(VC1DSPContext* dsp); > void ff_vc1dsp_init_loongarch(VC1DSPContext* dsp);
> Probably missing VLENB checks. Changed. > You can multiply by 3, 5 or 9 with shift-and-add. By 12 with shift-and-add > then shift, and by 17 with shift then add. You don't need multiplications. Changed. > Do you really need to splat? Can't .vx or .wx be used instead? Okay, for example in ff_vc1_inv_trans_8x8_dc_rvv + vsetvli zero, t0, e8, m2, ta, ma + vwaddu.vx v4, v0, zero + vsetvli zero, t0, e16, m4, ta, ma + vadd.vx v4, v4, t2 - vsetvli zero, t0, e16, m4, ta, ma - vmv.v.x v4, t2 - vsetvli zero, t0, e8, m2, ta, ma - vwaddu.wv v4, v4, v0 But the speed has slowed down slightly on the c910, I'm not sure if I should modify it. splat | no splat vc1dsp.vc1_inv_trans_4x4_dc_c: 84.0 | 84.0 vc1dsp.vc1_inv_trans_4x4_dc_rvv_i32: 74.0 | 76.0 vc1dsp.vc1_inv_trans_4x8_dc_c: 150.0 | 150.0 vc1dsp.vc1_inv_trans_4x8_dc_rvv_i32: 83.5 | 84.5 vc1dsp.vc1_inv_trans_8x4_dc_c: 129.0 | 129.0 vc1dsp.vc1_inv_trans_8x4_dc_rvv_i64: 76.0 | 76.7 vc1dsp.vc1_inv_trans_8x8_dc_c: 255.0 | 254.7 vc1dsp.vc1_inv_trans_8x8_dc_rvv_i64: 90.5 | 93.0 > The code below uses fractional multipliers, so I infer that the benchmarked > code was significantly different, and the measurements are not really worth the > bother. > > I know that supply is a problem at the moment, but I if you are going to keep > this up, I would hope that ISCAS can get you access to an RVV 1.0 board. Using mf2 only requires changing the first vset and the last vset in each function to mf2. I guess they would achieve similar effects on both c910 and c908? example in 8x8 ``` - vsetivli zero, 8, e64, m4, ta, ma + vsetivli zero, 8, e8, mf2, ta, ma - vsetvli zero, zero, e64, m4, ta, ma + vsetivli zero, 8, e8, mf2, ta, ma ``` And ISCAS seems to have no announcement about getting an RVV 1.0 board. I plan to ask about it from time to time. Rémi Denis-Courmont <remi@remlab.net> 于2023年12月4日周一 01:17写道： > Le sunnuntaina 3. joulukuuta 2023, 16.40.08 EET flow gg a écrit : > > c910 > > vc1dsp.vc1_inv_trans_4x4_dc_c: 84.0 > > vc1dsp.vc1_inv_trans_4x4_dc_rvv_i32: 74.0 > > vc1dsp.vc1_inv_trans_4x8_dc_c: 150.2 > > vc1dsp.vc1_inv_trans_4x8_dc_rvv_i32: 83.5 > > vc1dsp.vc1_inv_trans_8x4_dc_c: 129.0 > > vc1dsp.vc1_inv_trans_8x4_dc_rvv_i64: 75.7 > > vc1dsp.vc1_inv_trans_8x8_dc_c: 254.7 > > vc1dsp.vc1_inv_trans_8x8_dc_rvv_i64: 90.5 > > The code below uses fractional multipliers, so I infer that the > benchmarked > code was significantly different, and the measurements are not really > worth the > bother. > > I know that supply is a problem at the moment, but I if you are going to > keep > this up, I would hope that ISCAS can get you access to an RVV 1.0 board. > > In-line... > > > diff --git a/libavcodec/riscv/vc1dsp_init.c > b/libavcodec/riscv/vc1dsp_init.c > > new file mode 100644 > > index 0000000000..88e0434f0e > > --- /dev/null > > +++ b/libavcodec/riscv/vc1dsp_init.c > > @@ -0,0 +1,47 @@ > > +/* > > + * Copyright (c) 2023 Institue of Software Chinese Academy of Sciences > > (ISCAS). > > + * > > + * This file is part of FFmpeg. > > + * > > + * FFmpeg is free software; you can redistribute it and/or > > + * modify it under the terms of the GNU Lesser General Public > > + * License as published by the Free Software Foundation; either > > + * version 2.1 of the License, or (at your option) any later version. > > + * > > + * FFmpeg is distributed in the hope that it will be useful, > > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU > > + * Lesser General Public License for more details. > > + * > > + * You should have received a copy of the GNU Lesser General Public > > + * License along with FFmpeg; if not, write to the Free Software > > + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA > 02110-1301 > > USA > > + */ > > + > > +#include <stdint.h> > > + > > +#include "libavutil/attributes.h" > > +#include "libavutil/cpu.h" > > +#include "libavutil/riscv/cpu.h" > > +#include "libavcodec/vc1.h" > > + > > +void ff_vc1_inv_trans_8x8_dc_rvv(uint8_t *dest, ptrdiff_t stride, > int16_t > > *block); > > +void ff_vc1_inv_trans_4x8_dc_rvv(uint8_t *dest, ptrdiff_t stride, > int16_t > > *block); > > +void ff_vc1_inv_trans_8x4_dc_rvv(uint8_t *dest, ptrdiff_t stride, > int16_t > > *block); > > +void ff_vc1_inv_trans_4x4_dc_rvv(uint8_t *dest, ptrdiff_t stride, > int16_t > > *block); > > + > > +av_cold void ff_vc1dsp_init_riscv(VC1DSPContext *dsp) > > +{ > > +#if HAVE_RVV > > + int flags = av_get_cpu_flags(); > > + > > + if (flags & AV_CPU_FLAG_RVV_I64) { > > + dsp->vc1_inv_trans_8x8_dc = ff_vc1_inv_trans_8x8_dc_rvv; > > + dsp->vc1_inv_trans_8x4_dc = ff_vc1_inv_trans_8x4_dc_rvv; > > + } > > + if (flags & AV_CPU_FLAG_RVV_I32) { > > + dsp->vc1_inv_trans_4x8_dc = ff_vc1_inv_trans_4x8_dc_rvv; > > + dsp->vc1_inv_trans_4x4_dc = ff_vc1_inv_trans_4x4_dc_rvv; > > + } > > Probably missing VLENB checks. > > > +#endif > > +} > > diff --git a/libavcodec/riscv/vc1dsp_rvv.S > b/libavcodec/riscv/vc1dsp_rvv.S > > new file mode 100644 > > index 0000000000..8a6b27192a > > --- /dev/null > > +++ b/libavcodec/riscv/vc1dsp_rvv.S > > @@ -0,0 +1,123 @@ > > +/* > > + * Copyright (c) 2023 Institue of Software Chinese Academy of Sciences > > (ISCAS). > > + * > > + * This file is part of FFmpeg. > > + * > > + * FFmpeg is free software; you can redistribute it and/or > > + * modify it under the terms of the GNU Lesser General Public > > + * License as published by the Free Software Foundation; either > > + * version 2.1 of the License, or (at your option) any later version. > > + * > > + * FFmpeg is distributed in the hope that it will be useful, > > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU > > + * Lesser General Public License for more details. > > + * > > + * You should have received a copy of the GNU Lesser General Public > > + * License along with FFmpeg; if not, write to the Free Software > > + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA > 02110-1301 > > USA > > + */ > > + > > +#include "libavutil/riscv/asm.S" > > + > > +func ff_vc1_inv_trans_8x8_dc_rvv, zve64x > > + lh t2, (a2) > > + li t1, 3 > > + mul t2, t2, t1 > > You can multiply by 3, 5 or 9 with shift-and-add. By 12 with shift-and-add > then shift, and by 17 with shift then add. You don't need multiplications. > > > + addi t2, t2, 1 > > + srai t2, t2, 1 > > + mul t2, t2, t1 > > + addi t2, t2, 16 > > + srai t2, t2, 5 > > + vsetivli zero, 8, e8, mf2, ta, ma > > + vlse64.v v0, (a0), a1 > > + li t0, 8*8 > > + vsetvli zero, t0, e16, m8, ta, ma > > + vmv.v.x v8, t2 > > Do you really need to splat? Can't .vx or .wx be used instead? > > > + vsetvli zero, t0, e8, m4, ta, ma > > + vwaddu.wv v8, v8, v0 > > + vsetvli zero, t0, e16, m8, ta, ma > > + vmax.vx v8, v8, zero > > + vsetvli zero, t0, e8, m4, ta, ma > > + vnclipu.wi v0, v8, 0 > > + vsetivli zero, 8, e8, mf2, ta, ma > > + vsse64.v v0, (a0), a1 > > + ret > > +endfunc > > + > > +func ff_vc1_inv_trans_4x8_dc_rvv, zve32x > > + lh t2, (a2) > > + li t1, 17 > > + mul t2, t2, t1 > > + addi t2, t2, 4 > > + srai t2, t2, 3 > > + li t1, 12 > > + mul t2, t2, t1 > > + addi t2, t2, 64 > > + srai t2, t2, 7 > > + vsetivli zero, 8, e8, mf2, ta, ma > > + vlse32.v v0, (a0), a1 > > + li t0, 4*8 > > + vsetvli zero, t0, e16, m4, ta, ma > > + vmv.v.x v4, t2 > > + vsetvli zero, t0, e8, m2, ta, ma > > + vwaddu.wv v4, v4, v0 > > + vsetvli zero, t0, e16, m4, ta, ma > > + vmax.vx v4, v4, zero > > + vsetvli zero, t0, e8, m2, ta, ma > > + vnclipu.wi v0, v4, 0 > > + vsetivli zero, 8, e8, mf2, ta, ma > > + vsse32.v v0, (a0), a1 > > + ret > > +endfunc > > + > > +func ff_vc1_inv_trans_8x4_dc_rvv, zve64x > > + lh t2, (a2) > > + li t1, 3 > > + mul t2, t2, t1 > > + addi t2, t2, 1 > > + srai t2, t2, 1 > > + li t1, 17 > > + mul t2, t2, t1 > > + addi t2, t2, 64 > > + srai t2, t2, 7 > > + vsetivli zero, 8, e8, mf2, ta, ma > > + vlse64.v v0, (a0), a1 > > + li t0, 8*4 > > + vsetvli zero, t0, e16, m4, ta, ma > > + vmv.v.x v4, t2 > > + vsetvli zero, t0, e8, m2, ta, ma > > + vwaddu.wv v4, v4, v0 > > + vsetvli zero, t0, e16, m4, ta, ma > > + vmax.vx v4, v4, zero > > + vsetvli zero, t0, e8, m2, ta, ma > > + vnclipu.wi v0, v4, 0 > > + vsetivli zero, 8, e8, mf2, ta, ma > > + vsse64.v v0, (a0), a1 > > + ret > > +endfunc > > + > > +func ff_vc1_inv_trans_4x4_dc_rvv, zve32x > > + lh t2, (a2) > > + li t1, 17 > > + mul t2, t2, t1 > > + addi t2, t2, 4 > > + srai t2, t2, 3 > > + mul t2, t2, t1 > > + addi t2, t2, 64 > > + srai t2, t2, 7 > > + vsetivli zero, 4, e8, mf2, ta, ma > > + vlse32.v v0, (a0), a1 > > + li t0, 4*4 > > + vsetvli zero, t0, e16, m2, ta, ma > > + vmv.v.x v2, t2 > > + vsetvli zero, t0, e8, m1, ta, ma > > + vwaddu.wv v2, v2, v0 > > + vsetvli zero, t0, e16, m2, ta, ma > > + vmax.vx v2, v2, zero > > + vsetvli zero, t0, e8, m1, ta, ma > > + vnclipu.wi v0, v2, 0 > > + vsetivli zero, 4, e8, mf2, ta, ma > > + vsse32.v v0, (a0), a1 > > + ret > > +endfunc > > diff --git a/libavcodec/vc1dsp.c b/libavcodec/vc1dsp.c > > index 62c8eb21fa..2caa3c6863 100644 > > --- a/libavcodec/vc1dsp.c > > +++ b/libavcodec/vc1dsp.c > > @@ -1039,6 +1039,8 @@ av_cold void ff_vc1dsp_init(VC1DSPContext *dsp) > > ff_vc1dsp_init_arm(dsp); > > #elif ARCH_PPC > > ff_vc1dsp_init_ppc(dsp); > > +#elif ARCH_RISCV > > + ff_vc1dsp_init_riscv(dsp); > > #elif ARCH_X86 > > ff_vc1dsp_init_x86(dsp); > > #elif ARCH_MIPS > > diff --git a/libavcodec/vc1dsp.h b/libavcodec/vc1dsp.h > > index 7ed1776ca7..e3b90d2b62 100644 > > --- a/libavcodec/vc1dsp.h > > +++ b/libavcodec/vc1dsp.h > > @@ -89,6 +89,7 @@ void ff_vc1dsp_init(VC1DSPContext* c); > > void ff_vc1dsp_init_aarch64(VC1DSPContext* dsp); > > void ff_vc1dsp_init_arm(VC1DSPContext* dsp); > > void ff_vc1dsp_init_ppc(VC1DSPContext *c); > > +void ff_vc1dsp_init_riscv(VC1DSPContext *c); > > void ff_vc1dsp_init_x86(VC1DSPContext* dsp); > > void ff_vc1dsp_init_mips(VC1DSPContext* dsp); > > void ff_vc1dsp_init_loongarch(VC1DSPContext* dsp); > > -- > レミ・デニ-クールモン > http://www.remlab.net/ > > > > _______________________________________________ > ffmpeg-devel mailing list > ffmpeg-devel@ffmpeg.org > https://ffmpeg.org/mailman/listinfo/ffmpeg-devel > > To unsubscribe, visit link above, or email > ffmpeg-devel-request@ffmpeg.org with subject "unsubscribe". >
Le maanantaina 4. joulukuuta 2023, 10.48.56 EET flow gg a écrit : > > Probably missing VLENB checks. > > Changed. > > > You can multiply by 3, 5 or 9 with shift-and-add. By 12 with shift-and-add > > then shift, and by 17 with shift then add. You don't need multiplications. > > Changed. > > > Do you really need to splat? Can't .vx or .wx be used instead? > > Okay, for example in ff_vc1_inv_trans_8x8_dc_rvv > > + vsetvli zero, t0, e8, m2, ta, ma > + vwaddu.vx v4, v0, zero > + vsetvli zero, t0, e16, m4, ta, ma > + vadd.vx v4, v4, t2 > - vsetvli zero, t0, e16, m4, ta, ma > - vmv.v.x v4, t2 > - vsetvli zero, t0, e8, m2, ta, ma > - vwaddu.wv v4, v4, v0 > > But the speed has slowed down slightly on the c910, > I'm not sure if I should modify it. OK, unfortunately, there is no widening addition with wide scalar operand. But you can do zero-extension then addition here. In the end, I doubt that you can reasonably optimise whilst working with a C910-based board. This function deviates too much on non-conformant hardware.
I found that in the case of nosplat, an additional vset can be removed, and the time is basically the same, so I updated the patch. Rémi Denis-Courmont <remi@remlab.net> 于2023年12月4日周一 23:15写道： > Le maanantaina 4. joulukuuta 2023, 10.48.56 EET flow gg a écrit : > > > Probably missing VLENB checks. > > > > Changed. > > > > > You can multiply by 3, 5 or 9 with shift-and-add. By 12 with > shift-and-add > > > then shift, and by 17 with shift then add. You don't need > multiplications. > > > > Changed. > > > > > Do you really need to splat? Can't .vx or .wx be used instead? > > > > Okay, for example in ff_vc1_inv_trans_8x8_dc_rvv > > > > + vsetvli zero, t0, e8, m2, ta, ma > > + vwaddu.vx v4, v0, zero > > + vsetvli zero, t0, e16, m4, ta, ma > > + vadd.vx v4, v4, t2 > > - vsetvli zero, t0, e16, m4, ta, ma > > - vmv.v.x v4, t2 > > - vsetvli zero, t0, e8, m2, ta, ma > > - vwaddu.wv v4, v4, v0 > > > > But the speed has slowed down slightly on the c910, > > I'm not sure if I should modify it. > > OK, unfortunately, there is no widening addition with wide scalar operand. > But > you can do zero-extension then addition here. In the end, I doubt that you > can > reasonably optimise whilst working with a C910-based board. This function > deviates too much on non-conformant hardware. > > -- > レミ・デニ-クールモン > http://www.remlab.net/ > > > > _______________________________________________ > ffmpeg-devel mailing list > ffmpeg-devel@ffmpeg.org > https://ffmpeg.org/mailman/listinfo/ffmpeg-devel > > To unsubscribe, visit link above, or email > ffmpeg-devel-request@ffmpeg.org with subject "unsubscribe". >
Okay, after using zext, can delete two vset, which is better than splat. I have updated the patch in this reply. Rémi Denis-Courmont <remi@remlab.net> 于2023年12月4日周一 23:15写道： > Le maanantaina 4. joulukuuta 2023, 10.48.56 EET flow gg a écrit : > > > Probably missing VLENB checks. > > > > Changed. > > > > > You can multiply by 3, 5 or 9 with shift-and-add. By 12 with > shift-and-add > > > then shift, and by 17 with shift then add. You don't need > multiplications. > > > > Changed. > > > > > Do you really need to splat? Can't .vx or .wx be used instead? > > > > Okay, for example in ff_vc1_inv_trans_8x8_dc_rvv > > > > + vsetvli zero, t0, e8, m2, ta, ma > > + vwaddu.vx v4, v0, zero > > + vsetvli zero, t0, e16, m4, ta, ma > > + vadd.vx v4, v4, t2 > > - vsetvli zero, t0, e16, m4, ta, ma > > - vmv.v.x v4, t2 > > - vsetvli zero, t0, e8, m2, ta, ma > > - vwaddu.wv v4, v4, v0 > > > > But the speed has slowed down slightly on the c910, > > I'm not sure if I should modify it. > > OK, unfortunately, there is no widening addition with wide scalar operand. > But > you can do zero-extension then addition here. In the end, I doubt that you > can > reasonably optimise whilst working with a C910-based board. This function > deviates too much on non-conformant hardware. > > -- > レミ・デニ-クールモン > http://www.remlab.net/ > > > > _______________________________________________ > ffmpeg-devel mailing list > ffmpeg-devel@ffmpeg.org > https://ffmpeg.org/mailman/listinfo/ffmpeg-devel > > To unsubscribe, visit link above, or email > ffmpeg-devel-request@ffmpeg.org with subject "unsubscribe". >
Hi, > diff --git a/libavcodec/riscv/Makefile b/libavcodec/riscv/Makefile > index 2d0e6c19c8..442c5961ea 100644 > --- a/libavcodec/riscv/Makefile > +++ b/libavcodec/riscv/Makefile > @@ -39,5 +39,7 @@ OBJS-$(CONFIG_PIXBLOCKDSP) += riscv/pixblockdsp_init.o \ > RVV-OBJS-$(CONFIG_PIXBLOCKDSP) += riscv/pixblockdsp_rvv.o > OBJS-$(CONFIG_UTVIDEO_DECODER) += riscv/utvideodsp_init.o > RVV-OBJS-$(CONFIG_UTVIDEO_DECODER) += riscv/utvideodsp_rvv.o > +OBJS-$(CONFIG_VC1DSP) += riscv/vc1dsp_init.o > +RVV-OBJS-$(CONFIG_VC1DSP) += riscv/vc1dsp_rvv.o > OBJS-$(CONFIG_VORBIS_DECODER) += riscv/vorbisdsp_init.o > RVV-OBJS-$(CONFIG_VORBIS_DECODER) += riscv/vorbisdsp_rvv.o > diff --git a/libavcodec/riscv/vc1dsp_init.c b/libavcodec/riscv/vc1dsp_init.c > new file mode 100644 > index 0000000000..6a04bea6d6 > --- /dev/null > +++ b/libavcodec/riscv/vc1dsp_init.c > @@ -0,0 +1,47 @@ > +/* > + * Copyright (c) 2023 Institue of Software Chinese Academy of Sciences > (ISCAS). > + * > + * This file is part of FFmpeg. > + * > + * FFmpeg is free software; you can redistribute it and/or > + * modify it under the terms of the GNU Lesser General Public > + * License as published by the Free Software Foundation; either > + * version 2.1 of the License, or (at your option) any later version. > + * > + * FFmpeg is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU > + * Lesser General Public License for more details. > + * > + * You should have received a copy of the GNU Lesser General Public > + * License along with FFmpeg; if not, write to the Free Software > + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 > USA > + */ > + > +#include <stdint.h> > + > +#include "libavutil/attributes.h" > +#include "libavutil/cpu.h" > +#include "libavutil/riscv/cpu.h" > +#include "libavcodec/vc1.h" > + > +void ff_vc1_inv_trans_8x8_dc_rvv(uint8_t *dest, ptrdiff_t stride, int16_t > *block); > +void ff_vc1_inv_trans_4x8_dc_rvv(uint8_t *dest, ptrdiff_t stride, int16_t > *block); > +void ff_vc1_inv_trans_8x4_dc_rvv(uint8_t *dest, ptrdiff_t stride, int16_t > *block); > +void ff_vc1_inv_trans_4x4_dc_rvv(uint8_t *dest, ptrdiff_t stride, int16_t > *block); > + > +av_cold void ff_vc1dsp_init_riscv(VC1DSPContext *dsp) > +{ > +#if HAVE_RVV > + int flags = av_get_cpu_flags(); > + > + if ((flags & AV_CPU_FLAG_RVV_I64) && ff_get_rv_vlenb() >= 16) { > + dsp->vc1_inv_trans_8x8_dc = ff_vc1_inv_trans_8x8_dc_rvv; > + dsp->vc1_inv_trans_8x4_dc = ff_vc1_inv_trans_8x4_dc_rvv; > + } This block can be folded into the next. You don't need to check VLENB twice. > + if ((flags & AV_CPU_FLAG_RVV_I32) && ff_get_rv_vlenb() >= 16) { > + dsp->vc1_inv_trans_4x8_dc = ff_vc1_inv_trans_4x8_dc_rvv; > + dsp->vc1_inv_trans_4x4_dc = ff_vc1_inv_trans_4x4_dc_rvv; > + } > +#endif > +} > diff --git a/libavcodec/riscv/vc1dsp_rvv.S b/libavcodec/riscv/vc1dsp_rvv.S > new file mode 100644 > index 0000000000..b865bd2cbc > --- /dev/null > +++ b/libavcodec/riscv/vc1dsp_rvv.S > @@ -0,0 +1,114 @@ > +/* > + * Copyright (c) 2023 Institue of Software Chinese Academy of Sciences > (ISCAS). > + * > + * This file is part of FFmpeg. > + * > + * FFmpeg is free software; you can redistribute it and/or > + * modify it under the terms of the GNU Lesser General Public > + * License as published by the Free Software Foundation; either > + * version 2.1 of the License, or (at your option) any later version. > + * > + * FFmpeg is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU > + * Lesser General Public License for more details. > + * > + * You should have received a copy of the GNU Lesser General Public > + * License along with FFmpeg; if not, write to the Free Software > + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 > USA > + */ > + > +#include "libavutil/riscv/asm.S" > + > +func ff_vc1_inv_trans_8x8_dc_rvv, zve64x > + lh t2, (a2) > + sh1add t2, t2, t2 > + addi t2, t2, 1 > + srai t2, t2, 1 > + sh1add t2, t2, t2 > + addi t2, t2, 16 > + srai t2, t2, 5 > + vsetivli zero, 8, e8, mf2, ta, ma > + vlse64.v v0, (a0), a1 > + li t0, 8*8 > + vsetvli zero, t0, e16, m8, ta, ma Instruction scheduling could be better, especially on in-order CPUs. > + vzext.vf2 v8, v0 > + vadd.vx v8, v8, t2 > + vmax.vx v8, v8, zero > + vsetvli zero, t0, e8, m4, ta, ma You don't need to reset the AVL here, just pass zero. > + vnclipu.wi v0, v8, 0 > + vsetivli zero, 8, e8, mf2, ta, ma > + vsse64.v v0, (a0), a1 > + ret > +endfunc > + > +func ff_vc1_inv_trans_4x8_dc_rvv, zve32x > + lh t2, (a2) > + slli t1, t2, 4 > + add t2, t2, t1 > + addi t2, t2, 4 > + srai t2, t2, 3 > + sh1add t2, t2, t2 > + slli t2, t2, 2 > + addi t2, t2, 64 > + srai t2, t2, 7 > + vsetivli zero, 8, e8, mf2, ta, ma > + vlse32.v v0, (a0), a1 > + li t0, 4*8 > + vsetvli zero, t0, e16, m4, ta, ma > + vzext.vf2 v4, v0 > + vadd.vx v4, v4, t2 > + vmax.vx v4, v4, zero > + vsetvli zero, t0, e8, m2, ta, ma > + vnclipu.wi v0, v4, 0 > + vsetivli zero, 8, e8, mf2, ta, ma > + vsse32.v v0, (a0), a1 > + ret > +endfunc > + > +func ff_vc1_inv_trans_8x4_dc_rvv, zve64x > + lh t2, (a2) > + sh1add t2, t2, t2 > + addi t2, t2, 1 > + srai t2, t2, 1 > + slli t1, t2, 4 > + add t2, t2, t1 > + addi t2, t2, 64 > + srai t2, t2, 7 > + vsetivli zero, 8, e8, mf2, ta, ma > + vlse64.v v0, (a0), a1 > + li t0, 8*4 > + vsetvli zero, t0, e16, m4, ta, ma > + vzext.vf2 v4, v0 > + vadd.vx v4, v4, t2 > + vmax.vx v4, v4, zero > + vsetvli zero, t0, e8, m2, ta, ma > + vnclipu.wi v0, v4, 0 > + vsetivli zero, 8, e8, mf2, ta, ma > + vsse64.v v0, (a0), a1 > + ret > +endfunc > + > +func ff_vc1_inv_trans_4x4_dc_rvv, zve32x > + lh t2, (a2) > + slli t1, t2, 4 > + add t2, t2, t1 > + addi t2, t2, 4 > + srai t2, t2, 3 > + slli t1, t2, 4 > + add t2, t2, t1 > + addi t2, t2, 64 > + srai t2, t2, 7 > + vsetivli zero, 4, e8, mf2, ta, ma > + vlse32.v v0, (a0), a1 > + li t0, 4*4 > + vsetvli zero, t0, e16, m2, ta, ma vsetivli > + vzext.vf2 v2, v0 > + vadd.vx v2, v2, t2 > + vmax.vx v2, v2, zero > + vsetvli zero, t0, e8, m1, ta, ma > + vnclipu.wi v0, v2, 0 > + vsetivli zero, 4, e8, mf2, ta, ma > + vsse32.v v0, (a0), a1 > + ret > +endfunc > diff --git a/libavcodec/vc1dsp.c b/libavcodec/vc1dsp.c > index 62c8eb21fa..2caa3c6863 100644 > --- a/libavcodec/vc1dsp.c > +++ b/libavcodec/vc1dsp.c > @@ -1039,6 +1039,8 @@ av_cold void ff_vc1dsp_init(VC1DSPContext *dsp) > ff_vc1dsp_init_arm(dsp); > #elif ARCH_PPC > ff_vc1dsp_init_ppc(dsp); > +#elif ARCH_RISCV > + ff_vc1dsp_init_riscv(dsp); > #elif ARCH_X86 > ff_vc1dsp_init_x86(dsp); > #elif ARCH_MIPS > diff --git a/libavcodec/vc1dsp.h b/libavcodec/vc1dsp.h > index 7ed1776ca7..e3b90d2b62 100644 > --- a/libavcodec/vc1dsp.h > +++ b/libavcodec/vc1dsp.h > @@ -89,6 +89,7 @@ void ff_vc1dsp_init(VC1DSPContext* c); > void ff_vc1dsp_init_aarch64(VC1DSPContext* dsp); > void ff_vc1dsp_init_arm(VC1DSPContext* dsp); > void ff_vc1dsp_init_ppc(VC1DSPContext *c); > +void ff_vc1dsp_init_riscv(VC1DSPContext *c); > void ff_vc1dsp_init_x86(VC1DSPContext* dsp); > void ff_vc1dsp_init_mips(VC1DSPContext* dsp); > void ff_vc1dsp_init_loongarch(VC1DSPContext* dsp);
> This block can be folded into the next. You don't need to check VLENB twice. Changed. > Instruction scheduling could be better, especially on in-order CPUs. I put the vload at the front, and then proceeded with the t2 operation, but I'm not sure... > You don't need to reset the AVL here, just pass zero. Changed. > vsetivli Changed. Rémi Denis-Courmont <remi@remlab.net> 于2023年12月6日周三 00:41写道： > Hi, > > > diff --git a/libavcodec/riscv/Makefile b/libavcodec/riscv/Makefile > > index 2d0e6c19c8..442c5961ea 100644 > > --- a/libavcodec/riscv/Makefile > > +++ b/libavcodec/riscv/Makefile > > @@ -39,5 +39,7 @@ OBJS-$(CONFIG_PIXBLOCKDSP) += riscv/pixblockdsp_init.o > \ > > RVV-OBJS-$(CONFIG_PIXBLOCKDSP) += riscv/pixblockdsp_rvv.o > > OBJS-$(CONFIG_UTVIDEO_DECODER) += riscv/utvideodsp_init.o > > RVV-OBJS-$(CONFIG_UTVIDEO_DECODER) += riscv/utvideodsp_rvv.o > > +OBJS-$(CONFIG_VC1DSP) += riscv/vc1dsp_init.o > > +RVV-OBJS-$(CONFIG_VC1DSP) += riscv/vc1dsp_rvv.o > > OBJS-$(CONFIG_VORBIS_DECODER) += riscv/vorbisdsp_init.o > > RVV-OBJS-$(CONFIG_VORBIS_DECODER) += riscv/vorbisdsp_rvv.o > > diff --git a/libavcodec/riscv/vc1dsp_init.c > b/libavcodec/riscv/vc1dsp_init.c > > new file mode 100644 > > index 0000000000..6a04bea6d6 > > --- /dev/null > > +++ b/libavcodec/riscv/vc1dsp_init.c > > @@ -0,0 +1,47 @@ > > +/* > > + * Copyright (c) 2023 Institue of Software Chinese Academy of Sciences > > (ISCAS). > > + * > > + * This file is part of FFmpeg. > > + * > > + * FFmpeg is free software; you can redistribute it and/or > > + * modify it under the terms of the GNU Lesser General Public > > + * License as published by the Free Software Foundation; either > > + * version 2.1 of the License, or (at your option) any later version. > > + * > > + * FFmpeg is distributed in the hope that it will be useful, > > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU > > + * Lesser General Public License for more details. > > + * > > + * You should have received a copy of the GNU Lesser General Public > > + * License along with FFmpeg; if not, write to the Free Software > > + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA > 02110-1301 > > USA > > + */ > > + > > +#include <stdint.h> > > + > > +#include "libavutil/attributes.h" > > +#include "libavutil/cpu.h" > > +#include "libavutil/riscv/cpu.h" > > +#include "libavcodec/vc1.h" > > + > > +void ff_vc1_inv_trans_8x8_dc_rvv(uint8_t *dest, ptrdiff_t stride, > int16_t > > *block); > > +void ff_vc1_inv_trans_4x8_dc_rvv(uint8_t *dest, ptrdiff_t stride, > int16_t > > *block); > > +void ff_vc1_inv_trans_8x4_dc_rvv(uint8_t *dest, ptrdiff_t stride, > int16_t > > *block); > > +void ff_vc1_inv_trans_4x4_dc_rvv(uint8_t *dest, ptrdiff_t stride, > int16_t > > *block); > > + > > +av_cold void ff_vc1dsp_init_riscv(VC1DSPContext *dsp) > > +{ > > +#if HAVE_RVV > > + int flags = av_get_cpu_flags(); > > + > > + if ((flags & AV_CPU_FLAG_RVV_I64) && ff_get_rv_vlenb() >= 16) { > > + dsp->vc1_inv_trans_8x8_dc = ff_vc1_inv_trans_8x8_dc_rvv; > > + dsp->vc1_inv_trans_8x4_dc = ff_vc1_inv_trans_8x4_dc_rvv; > > + } > > This block can be folded into the next. You don't need to check VLENB > twice. > > > + if ((flags & AV_CPU_FLAG_RVV_I32) && ff_get_rv_vlenb() >= 16) { > > + dsp->vc1_inv_trans_4x8_dc = ff_vc1_inv_trans_4x8_dc_rvv; > > + dsp->vc1_inv_trans_4x4_dc = ff_vc1_inv_trans_4x4_dc_rvv; > > + } > > +#endif > > +} > > diff --git a/libavcodec/riscv/vc1dsp_rvv.S > b/libavcodec/riscv/vc1dsp_rvv.S > > new file mode 100644 > > index 0000000000..b865bd2cbc > > --- /dev/null > > +++ b/libavcodec/riscv/vc1dsp_rvv.S > > @@ -0,0 +1,114 @@ > > +/* > > + * Copyright (c) 2023 Institue of Software Chinese Academy of Sciences > > (ISCAS). > > + * > > + * This file is part of FFmpeg. > > + * > > + * FFmpeg is free software; you can redistribute it and/or > > + * modify it under the terms of the GNU Lesser General Public > > + * License as published by the Free Software Foundation; either > > + * version 2.1 of the License, or (at your option) any later version. > > + * > > + * FFmpeg is distributed in the hope that it will be useful, > > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU > > + * Lesser General Public License for more details. > > + * > > + * You should have received a copy of the GNU Lesser General Public > > + * License along with FFmpeg; if not, write to the Free Software > > + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA > 02110-1301 > > USA > > + */ > > + > > +#include "libavutil/riscv/asm.S" > > + > > +func ff_vc1_inv_trans_8x8_dc_rvv, zve64x > > + lh t2, (a2) > > + sh1add t2, t2, t2 > > + addi t2, t2, 1 > > + srai t2, t2, 1 > > + sh1add t2, t2, t2 > > + addi t2, t2, 16 > > + srai t2, t2, 5 > > + vsetivli zero, 8, e8, mf2, ta, ma > > + vlse64.v v0, (a0), a1 > > + li t0, 8*8 > > + vsetvli zero, t0, e16, m8, ta, ma > > Instruction scheduling could be better, especially on in-order CPUs. > > > + vzext.vf2 v8, v0 > > + vadd.vx v8, v8, t2 > > + vmax.vx v8, v8, zero > > + vsetvli zero, t0, e8, m4, ta, ma > > You don't need to reset the AVL here, just pass zero. > > > + vnclipu.wi v0, v8, 0 > > + vsetivli zero, 8, e8, mf2, ta, ma > > + vsse64.v v0, (a0), a1 > > + ret > > +endfunc > > + > > +func ff_vc1_inv_trans_4x8_dc_rvv, zve32x > > + lh t2, (a2) > > + slli t1, t2, 4 > > + add t2, t2, t1 > > + addi t2, t2, 4 > > + srai t2, t2, 3 > > + sh1add t2, t2, t2 > > + slli t2, t2, 2 > > + addi t2, t2, 64 > > + srai t2, t2, 7 > > + vsetivli zero, 8, e8, mf2, ta, ma > > + vlse32.v v0, (a0), a1 > > + li t0, 4*8 > > + vsetvli zero, t0, e16, m4, ta, ma > > + vzext.vf2 v4, v0 > > + vadd.vx v4, v4, t2 > > + vmax.vx v4, v4, zero > > + vsetvli zero, t0, e8, m2, ta, ma > > + vnclipu.wi v0, v4, 0 > > + vsetivli zero, 8, e8, mf2, ta, ma > > + vsse32.v v0, (a0), a1 > > + ret > > +endfunc > > + > > +func ff_vc1_inv_trans_8x4_dc_rvv, zve64x > > + lh t2, (a2) > > + sh1add t2, t2, t2 > > + addi t2, t2, 1 > > + srai t2, t2, 1 > > + slli t1, t2, 4 > > + add t2, t2, t1 > > + addi t2, t2, 64 > > + srai t2, t2, 7 > > + vsetivli zero, 8, e8, mf2, ta, ma > > + vlse64.v v0, (a0), a1 > > + li t0, 8*4 > > + vsetvli zero, t0, e16, m4, ta, ma > > + vzext.vf2 v4, v0 > > + vadd.vx v4, v4, t2 > > + vmax.vx v4, v4, zero > > + vsetvli zero, t0, e8, m2, ta, ma > > + vnclipu.wi v0, v4, 0 > > + vsetivli zero, 8, e8, mf2, ta, ma > > + vsse64.v v0, (a0), a1 > > + ret > > +endfunc > > + > > +func ff_vc1_inv_trans_4x4_dc_rvv, zve32x > > + lh t2, (a2) > > + slli t1, t2, 4 > > + add t2, t2, t1 > > + addi t2, t2, 4 > > + srai t2, t2, 3 > > + slli t1, t2, 4 > > + add t2, t2, t1 > > + addi t2, t2, 64 > > + srai t2, t2, 7 > > + vsetivli zero, 4, e8, mf2, ta, ma > > + vlse32.v v0, (a0), a1 > > + li t0, 4*4 > > + vsetvli zero, t0, e16, m2, ta, ma > > vsetivli > > > + vzext.vf2 v2, v0 > > + vadd.vx v2, v2, t2 > > + vmax.vx v2, v2, zero > > + vsetvli zero, t0, e8, m1, ta, ma > > + vnclipu.wi v0, v2, 0 > > + vsetivli zero, 4, e8, mf2, ta, ma > > + vsse32.v v0, (a0), a1 > > + ret > > +endfunc > > diff --git a/libavcodec/vc1dsp.c b/libavcodec/vc1dsp.c > > index 62c8eb21fa..2caa3c6863 100644 > > --- a/libavcodec/vc1dsp.c > > +++ b/libavcodec/vc1dsp.c > > @@ -1039,6 +1039,8 @@ av_cold void ff_vc1dsp_init(VC1DSPContext *dsp) > > ff_vc1dsp_init_arm(dsp); > > #elif ARCH_PPC > > ff_vc1dsp_init_ppc(dsp); > > +#elif ARCH_RISCV > > + ff_vc1dsp_init_riscv(dsp); > > #elif ARCH_X86 > > ff_vc1dsp_init_x86(dsp); > > #elif ARCH_MIPS > > diff --git a/libavcodec/vc1dsp.h b/libavcodec/vc1dsp.h > > index 7ed1776ca7..e3b90d2b62 100644 > > --- a/libavcodec/vc1dsp.h > > +++ b/libavcodec/vc1dsp.h > > @@ -89,6 +89,7 @@ void ff_vc1dsp_init(VC1DSPContext* c); > > void ff_vc1dsp_init_aarch64(VC1DSPContext* dsp); > > void ff_vc1dsp_init_arm(VC1DSPContext* dsp); > > void ff_vc1dsp_init_ppc(VC1DSPContext *c); > > +void ff_vc1dsp_init_riscv(VC1DSPContext *c); > > void ff_vc1dsp_init_x86(VC1DSPContext* dsp); > > void ff_vc1dsp_init_mips(VC1DSPContext* dsp); > > void ff_vc1dsp_init_loongarch(VC1DSPContext* dsp); > > > -- > Rémi Denis-Courmont > http://www.remlab.net/ > > > > _______________________________________________ > ffmpeg-devel mailing list > ffmpeg-devel@ffmpeg.org > https://ffmpeg.org/mailman/listinfo/ffmpeg-devel > > To unsubscribe, visit link above, or email > ffmpeg-devel-request@ffmpeg.org with subject "unsubscribe". >
Le tiistaina 5. joulukuuta 2023, 21.25.12 EET flow gg a écrit : > > This block can be folded into the next. You don't need to check VLENB > > twice. > > Changed. > > > Instruction scheduling could be better, especially on in-order CPUs. > > I put the vload at the front, and then proceeded with the t2 operation, but > I'm not sure... > > > You don't need to reset the AVL here, just pass zero. > > Changed. > > > vsetivli > > Changed. You changed more than I asked for. The immediate AVL is a 5-bit unsigned integer, so it should not be possible to assemble 32 or 64, unless you have a preprocessor that silently rewrites `vsetivli` into `vsetvli` (If so, that sounds very iffy because `vsetivli zero` has no scratch X register to work with). FWIW CanMV-K230 boards are on sale for under 500 RMB.
I'm sorry for my carelessness.It's because I used to build and run manually, but now I've switched to a script to do it, so I accidentally missed the error.I will modify the script and to avoid this kind of issue in the future. libavcodec/riscv/vc1dsp_rvv.S:35: Error: improper CSRxI immediate Changed. Rémi Denis-Courmont <remi@remlab.net> 于2023年12月6日周三 04:11写道： > Le tiistaina 5. joulukuuta 2023, 21.25.12 EET flow gg a écrit : > > > This block can be folded into the next. You don't need to check VLENB > > > > twice. > > > > Changed. > > > > > Instruction scheduling could be better, especially on in-order CPUs. > > > > I put the vload at the front, and then proceeded with the t2 operation, > but > > I'm not sure... > > > > > You don't need to reset the AVL here, just pass zero. > > > > Changed. > > > > > vsetivli > > > > Changed. > > You changed more than I asked for. The immediate AVL is a 5-bit unsigned > integer, so it should not be possible to assemble 32 or 64, unless you > have a > preprocessor that silently rewrites `vsetivli` into `vsetvli` (If so, that > sounds very iffy because `vsetivli zero` has no scratch X register to work > with). > > FWIW CanMV-K230 boards are on sale for under 500 RMB. > > -- > レミ・デニ-クールモン > http://www.remlab.net/ > > > > _______________________________________________ > ffmpeg-devel mailing list > ffmpeg-devel@ffmpeg.org > https://ffmpeg.org/mailman/listinfo/ffmpeg-devel > > To unsubscribe, visit link above, or email > ffmpeg-devel-request@ffmpeg.org with subject "unsubscribe". >
> FWIW CanMV-K230 boards are on sale for under 500 RMB. I just made a payment ~ （I saw you mention in IRC that you're going to write about K230+Debian. Looking forward to it） Rémi Denis-Courmont <remi@remlab.net> 于2023年12月6日周三 04:11写道： > Le tiistaina 5. joulukuuta 2023, 21.25.12 EET flow gg a écrit : > > > This block can be folded into the next. You don't need to check VLENB > > > > twice. > > > > Changed. > > > > > Instruction scheduling could be better, especially on in-order CPUs. > > > > I put the vload at the front, and then proceeded with the t2 operation, > but > > I'm not sure... > > > > > You don't need to reset the AVL here, just pass zero. > > > > Changed. > > > > > vsetivli > > > > Changed. > > You changed more than I asked for. The immediate AVL is a 5-bit unsigned > integer, so it should not be possible to assemble 32 or 64, unless you > have a > preprocessor that silently rewrites `vsetivli` into `vsetvli` (If so, that > sounds very iffy because `vsetivli zero` has no scratch X register to work > with). > > FWIW CanMV-K230 boards are on sale for under 500 RMB. > > -- > レミ・デニ-クールモン > http://www.remlab.net/ > > > > _______________________________________________ > ffmpeg-devel mailing list > ffmpeg-devel@ffmpeg.org > https://ffmpeg.org/mailman/listinfo/ffmpeg-devel > > To unsubscribe, visit link above, or email > ffmpeg-devel-request@ffmpeg.org with subject "unsubscribe". >
Hello, I have received the K230, and then installed Debian following your
method. Therefore, I have updated the benchmark of K230 in the patch of
this reply.
k230
vc1dsp.vc1_inv_trans_4x4_dc_c: 125.7
vc1dsp.vc1_inv_trans_4x4_dc_rvv_i32: 53.5
vc1dsp.vc1_inv_trans_4x8_dc_c: 230.7
vc1dsp.vc1_inv_trans_4x8_dc_rvv_i32: 65.5
vc1dsp.vc1_inv_trans_8x4_dc_c: 228.7
vc1dsp.vc1_inv_trans_8x4_dc_rvv_i64: 64.5
vc1dsp.vc1_inv_trans_8x8_dc_c: 476.5
vc1dsp.vc1_inv_trans_8x8_dc_rvv_i64: 80.2
Rémi Denis-Courmont <remi@remlab.net> 于2023年12月4日周一 01:17写道：
> Le sunnuntaina 3. joulukuuta 2023, 16.40.08 EET flow gg a écrit :
> > c910
> > vc1dsp.vc1_inv_trans_4x4_dc_c: 84.0
> > vc1dsp.vc1_inv_trans_4x4_dc_rvv_i32: 74.0
> > vc1dsp.vc1_inv_trans_4x8_dc_c: 150.2
> > vc1dsp.vc1_inv_trans_4x8_dc_rvv_i32: 83.5
> > vc1dsp.vc1_inv_trans_8x4_dc_c: 129.0
> > vc1dsp.vc1_inv_trans_8x4_dc_rvv_i64: 75.7
> > vc1dsp.vc1_inv_trans_8x8_dc_c: 254.7
> > vc1dsp.vc1_inv_trans_8x8_dc_rvv_i64: 90.5
>
> The code below uses fractional multipliers, so I infer that the
> benchmarked
> code was significantly different, and the measurements are not really
> worth the
> bother.
>
> I know that supply is a problem at the moment, but I if you are going to
> keep
> this up, I would hope that ISCAS can get you access to an RVV 1.0 board.
>
> In-line...
>
> > diff --git a/libavcodec/riscv/vc1dsp_init.c
> b/libavcodec/riscv/vc1dsp_init.c
> > new file mode 100644
> > index 0000000000..88e0434f0e
> > --- /dev/null
> > +++ b/libavcodec/riscv/vc1dsp_init.c
> > @@ -0,0 +1,47 @@
> > +/*
> > + * Copyright (c) 2023 Institue of Software Chinese Academy of Sciences
> > (ISCAS).
> > + *
> > + * This file is part of FFmpeg.
> > + *
> > + * FFmpeg is free software; you can redistribute it and/or
> > + * modify it under the terms of the GNU Lesser General Public
> > + * License as published by the Free Software Foundation; either
> > + * version 2.1 of the License, or (at your option) any later version.
> > + *
> > + * FFmpeg is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
> > + * Lesser General Public License for more details.
> > + *
> > + * You should have received a copy of the GNU Lesser General Public
> > + * License along with FFmpeg; if not, write to the Free Software
> > + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
> 02110-1301
> > USA
> > + */
> > +
> > +#include <stdint.h>
> > +
> > +#include "libavutil/attributes.h"
> > +#include "libavutil/cpu.h"
> > +#include "libavutil/riscv/cpu.h"
> > +#include "libavcodec/vc1.h"
> > +
> > +void ff_vc1_inv_trans_8x8_dc_rvv(uint8_t *dest, ptrdiff_t stride,
> int16_t
> > *block);
> > +void ff_vc1_inv_trans_4x8_dc_rvv(uint8_t *dest, ptrdiff_t stride,
> int16_t
> > *block);
> > +void ff_vc1_inv_trans_8x4_dc_rvv(uint8_t *dest, ptrdiff_t stride,
> int16_t
> > *block);
> > +void ff_vc1_inv_trans_4x4_dc_rvv(uint8_t *dest, ptrdiff_t stride,
> int16_t
> > *block);
> > +
> > +av_cold void ff_vc1dsp_init_riscv(VC1DSPContext *dsp)
> > +{
> > +#if HAVE_RVV
> > + int flags = av_get_cpu_flags();
> > +
> > + if (flags & AV_CPU_FLAG_RVV_I64) {
> > + dsp->vc1_inv_trans_8x8_dc = ff_vc1_inv_trans_8x8_dc_rvv;
> > + dsp->vc1_inv_trans_8x4_dc = ff_vc1_inv_trans_8x4_dc_rvv;
> > + }
> > + if (flags & AV_CPU_FLAG_RVV_I32) {
> > + dsp->vc1_inv_trans_4x8_dc = ff_vc1_inv_trans_4x8_dc_rvv;
> > + dsp->vc1_inv_trans_4x4_dc = ff_vc1_inv_trans_4x4_dc_rvv;
> > + }
>
> Probably missing VLENB checks.
>
> > +#endif
> > +}
> > diff --git a/libavcodec/riscv/vc1dsp_rvv.S
> b/libavcodec/riscv/vc1dsp_rvv.S
> > new file mode 100644
> > index 0000000000..8a6b27192a
> > --- /dev/null
> > +++ b/libavcodec/riscv/vc1dsp_rvv.S
> > @@ -0,0 +1,123 @@
> > +/*
> > + * Copyright (c) 2023 Institue of Software Chinese Academy of Sciences
> > (ISCAS).
> > + *
> > + * This file is part of FFmpeg.
> > + *
> > + * FFmpeg is free software; you can redistribute it and/or
> > + * modify it under the terms of the GNU Lesser General Public
> > + * License as published by the Free Software Foundation; either
> > + * version 2.1 of the License, or (at your option) any later version.
> > + *
> > + * FFmpeg is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
> > + * Lesser General Public License for more details.
> > + *
> > + * You should have received a copy of the GNU Lesser General Public
> > + * License along with FFmpeg; if not, write to the Free Software
> > + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
> 02110-1301
> > USA
> > + */
> > +
> > +#include "libavutil/riscv/asm.S"
> > +
> > +func ff_vc1_inv_trans_8x8_dc_rvv, zve64x
> > + lh t2, (a2)
> > + li t1, 3
> > + mul t2, t2, t1
>
> You can multiply by 3, 5 or 9 with shift-and-add. By 12 with shift-and-add
> then shift, and by 17 with shift then add. You don't need multiplications.
>
> > + addi t2, t2, 1
> > + srai t2, t2, 1
> > + mul t2, t2, t1
> > + addi t2, t2, 16
> > + srai t2, t2, 5
> > + vsetivli zero, 8, e8, mf2, ta, ma
> > + vlse64.v v0, (a0), a1
> > + li t0, 8*8
> > + vsetvli zero, t0, e16, m8, ta, ma
> > + vmv.v.x v8, t2
>
> Do you really need to splat? Can't .vx or .wx be used instead?
>
> > + vsetvli zero, t0, e8, m4, ta, ma
> > + vwaddu.wv v8, v8, v0
> > + vsetvli zero, t0, e16, m8, ta, ma
> > + vmax.vx v8, v8, zero
> > + vsetvli zero, t0, e8, m4, ta, ma
> > + vnclipu.wi v0, v8, 0
> > + vsetivli zero, 8, e8, mf2, ta, ma
> > + vsse64.v v0, (a0), a1
> > + ret
> > +endfunc
> > +
> > +func ff_vc1_inv_trans_4x8_dc_rvv, zve32x
> > + lh t2, (a2)
> > + li t1, 17
> > + mul t2, t2, t1
> > + addi t2, t2, 4
> > + srai t2, t2, 3
> > + li t1, 12
> > + mul t2, t2, t1
> > + addi t2, t2, 64
> > + srai t2, t2, 7
> > + vsetivli zero, 8, e8, mf2, ta, ma
> > + vlse32.v v0, (a0), a1
> > + li t0, 4*8
> > + vsetvli zero, t0, e16, m4, ta, ma
> > + vmv.v.x v4, t2
> > + vsetvli zero, t0, e8, m2, ta, ma
> > + vwaddu.wv v4, v4, v0
> > + vsetvli zero, t0, e16, m4, ta, ma
> > + vmax.vx v4, v4, zero
> > + vsetvli zero, t0, e8, m2, ta, ma
> > + vnclipu.wi v0, v4, 0
> > + vsetivli zero, 8, e8, mf2, ta, ma
> > + vsse32.v v0, (a0), a1
> > + ret
> > +endfunc
> > +
> > +func ff_vc1_inv_trans_8x4_dc_rvv, zve64x
> > + lh t2, (a2)
> > + li t1, 3
> > + mul t2, t2, t1
> > + addi t2, t2, 1
> > + srai t2, t2, 1
> > + li t1, 17
> > + mul t2, t2, t1
> > + addi t2, t2, 64
> > + srai t2, t2, 7
> > + vsetivli zero, 8, e8, mf2, ta, ma
> > + vlse64.v v0, (a0), a1
> > + li t0, 8*4
> > + vsetvli zero, t0, e16, m4, ta, ma
> > + vmv.v.x v4, t2
> > + vsetvli zero, t0, e8, m2, ta, ma
> > + vwaddu.wv v4, v4, v0
> > + vsetvli zero, t0, e16, m4, ta, ma
> > + vmax.vx v4, v4, zero
> > + vsetvli zero, t0, e8, m2, ta, ma
> > + vnclipu.wi v0, v4, 0
> > + vsetivli zero, 8, e8, mf2, ta, ma
> > + vsse64.v v0, (a0), a1
> > + ret
> > +endfunc
> > +
> > +func ff_vc1_inv_trans_4x4_dc_rvv, zve32x
> > + lh t2, (a2)
> > + li t1, 17
> > + mul t2, t2, t1
> > + addi t2, t2, 4
> > + srai t2, t2, 3
> > + mul t2, t2, t1
> > + addi t2, t2, 64
> > + srai t2, t2, 7
> > + vsetivli zero, 4, e8, mf2, ta, ma
> > + vlse32.v v0, (a0), a1
> > + li t0, 4*4
> > + vsetvli zero, t0, e16, m2, ta, ma
> > + vmv.v.x v2, t2
> > + vsetvli zero, t0, e8, m1, ta, ma
> > + vwaddu.wv v2, v2, v0
> > + vsetvli zero, t0, e16, m2, ta, ma
> > + vmax.vx v2, v2, zero
> > + vsetvli zero, t0, e8, m1, ta, ma
> > + vnclipu.wi v0, v2, 0
> > + vsetivli zero, 4, e8, mf2, ta, ma
> > + vsse32.v v0, (a0), a1
> > + ret
> > +endfunc
> > diff --git a/libavcodec/vc1dsp.c b/libavcodec/vc1dsp.c
> > index 62c8eb21fa..2caa3c6863 100644
> > --- a/libavcodec/vc1dsp.c
> > +++ b/libavcodec/vc1dsp.c
> > @@ -1039,6 +1039,8 @@ av_cold void ff_vc1dsp_init(VC1DSPContext *dsp)
> > ff_vc1dsp_init_arm(dsp);
> > #elif ARCH_PPC
> > ff_vc1dsp_init_ppc(dsp);
> > +#elif ARCH_RISCV
> > + ff_vc1dsp_init_riscv(dsp);
> > #elif ARCH_X86
> > ff_vc1dsp_init_x86(dsp);
> > #elif ARCH_MIPS
> > diff --git a/libavcodec/vc1dsp.h b/libavcodec/vc1dsp.h
> > index 7ed1776ca7..e3b90d2b62 100644
> > --- a/libavcodec/vc1dsp.h
> > +++ b/libavcodec/vc1dsp.h
> > @@ -89,6 +89,7 @@ void ff_vc1dsp_init(VC1DSPContext* c);
> > void ff_vc1dsp_init_aarch64(VC1DSPContext* dsp);
> > void ff_vc1dsp_init_arm(VC1DSPContext* dsp);
> > void ff_vc1dsp_init_ppc(VC1DSPContext *c);
> > +void ff_vc1dsp_init_riscv(VC1DSPContext *c);
> > void ff_vc1dsp_init_x86(VC1DSPContext* dsp);
> > void ff_vc1dsp_init_mips(VC1DSPContext* dsp);
> > void ff_vc1dsp_init_loongarch(VC1DSPContext* dsp);
>
> --
> レミ・デニ-クールモン
> http://www.remlab.net/
>
>
>
> _______________________________________________
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> https://ffmpeg.org/mailman/listinfo/ffmpeg-devel
>
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> ffmpeg-devel-request@ffmpeg.org with subject "unsubscribe".
>
From cba93503a6f0753b56c1d0cb00f642b3982ee656 Mon Sep 17 00:00:00 2001
From: sunyuechi <sunyuechi@iscas.ac.cn>
Date: Fri, 1 Dec 2023 10:07:40 +0800
Subject: [PATCH] lavc/vc1dsp: R-V V inv_trans
c910
vc1dsp.vc1_inv_trans_4x4_dc_c: 84.0
vc1dsp.vc1_inv_trans_4x4_dc_rvv_i32: 74.0
vc1dsp.vc1_inv_trans_4x8_dc_c: 150.2
vc1dsp.vc1_inv_trans_4x8_dc_rvv_i32: 83.5
vc1dsp.vc1_inv_trans_8x4_dc_c: 129.0
vc1dsp.vc1_inv_trans_8x4_dc_rvv_i64: 75.7
vc1dsp.vc1_inv_trans_8x8_dc_c: 254.7
vc1dsp.vc1_inv_trans_8x8_dc_rvv_i64: 90.5
---
libavcodec/riscv/Makefile | 2 +
libavcodec/riscv/vc1dsp_init.c | 47 +++++++++++++
libavcodec/riscv/vc1dsp_rvv.S | 123 +++++++++++++++++++++++++++++++++
libavcodec/vc1dsp.c | 2 +
libavcodec/vc1dsp.h | 1 +
5 files changed, 175 insertions(+)
create mode 100644 libavcodec/riscv/vc1dsp_init.c
create mode 100644 libavcodec/riscv/vc1dsp_rvv.S
diff --git a/libavcodec/riscv/Makefile b/libavcodec/riscv/Makefile
index 2d0e6c19c8..442c5961ea 100644
--- a/libavcodec/riscv/Makefile
+++ b/libavcodec/riscv/Makefile
@@ -39,5 +39,7 @@ OBJS-$(CONFIG_PIXBLOCKDSP) += riscv/pixblockdsp_init.o \
RVV-OBJS-$(CONFIG_PIXBLOCKDSP) += riscv/pixblockdsp_rvv.o
OBJS-$(CONFIG_UTVIDEO_DECODER) += riscv/utvideodsp_init.o
RVV-OBJS-$(CONFIG_UTVIDEO_DECODER) += riscv/utvideodsp_rvv.o
+OBJS-$(CONFIG_VC1DSP) += riscv/vc1dsp_init.o
+RVV-OBJS-$(CONFIG_VC1DSP) += riscv/vc1dsp_rvv.o
OBJS-$(CONFIG_VORBIS_DECODER) += riscv/vorbisdsp_init.o
RVV-OBJS-$(CONFIG_VORBIS_DECODER) += riscv/vorbisdsp_rvv.o
diff --git a/libavcodec/riscv/vc1dsp_init.c b/libavcodec/riscv/vc1dsp_init.c
new file mode 100644
index 0000000000..88e0434f0e
--- /dev/null
+++ b/libavcodec/riscv/vc1dsp_init.c
@@ -0,0 +1,47 @@
+/*
+ * Copyright (c) 2023 Institue of Software Chinese Academy of Sciences (ISCAS).
+ *
+ * This file is part of FFmpeg.
+ *
+ * FFmpeg is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2.1 of the License, or (at your option) any later version.
+ *
+ * FFmpeg is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with FFmpeg; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <stdint.h>
+
+#include "libavutil/attributes.h"
+#include "libavutil/cpu.h"
+#include "libavutil/riscv/cpu.h"
+#include "libavcodec/vc1.h"
+
+void ff_vc1_inv_trans_8x8_dc_rvv(uint8_t *dest, ptrdiff_t stride, int16_t *block);
+void ff_vc1_inv_trans_4x8_dc_rvv(uint8_t *dest, ptrdiff_t stride, int16_t *block);
+void ff_vc1_inv_trans_8x4_dc_rvv(uint8_t *dest, ptrdiff_t stride, int16_t *block);
+void ff_vc1_inv_trans_4x4_dc_rvv(uint8_t *dest, ptrdiff_t stride, int16_t *block);
+
+av_cold void ff_vc1dsp_init_riscv(VC1DSPContext *dsp)
+{
+#if HAVE_RVV
+ int flags = av_get_cpu_flags();
+
+ if (flags & AV_CPU_FLAG_RVV_I64) {
+ dsp->vc1_inv_trans_8x8_dc = ff_vc1_inv_trans_8x8_dc_rvv;
+ dsp->vc1_inv_trans_8x4_dc = ff_vc1_inv_trans_8x4_dc_rvv;
+ }
+ if (flags & AV_CPU_FLAG_RVV_I32) {
+ dsp->vc1_inv_trans_4x8_dc = ff_vc1_inv_trans_4x8_dc_rvv;
+ dsp->vc1_inv_trans_4x4_dc = ff_vc1_inv_trans_4x4_dc_rvv;
+ }
+#endif
+}
diff --git a/libavcodec/riscv/vc1dsp_rvv.S b/libavcodec/riscv/vc1dsp_rvv.S
new file mode 100644
index 0000000000..8a6b27192a
--- /dev/null
+++ b/libavcodec/riscv/vc1dsp_rvv.S
@@ -0,0 +1,123 @@
+/*
+ * Copyright (c) 2023 Institue of Software Chinese Academy of Sciences (ISCAS).
+ *
+ * This file is part of FFmpeg.
+ *
+ * FFmpeg is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2.1 of the License, or (at your option) any later version.
+ *
+ * FFmpeg is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with FFmpeg; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include "libavutil/riscv/asm.S"
+
+func ff_vc1_inv_trans_8x8_dc_rvv, zve64x
+ lh t2, (a2)
+ li t1, 3
+ mul t2, t2, t1
+ addi t2, t2, 1
+ srai t2, t2, 1
+ mul t2, t2, t1
+ addi t2, t2, 16
+ srai t2, t2, 5
+ vsetivli zero, 8, e8, mf2, ta, ma
+ vlse64.v v0, (a0), a1
+ li t0, 8*8
+ vsetvli zero, t0, e16, m8, ta, ma
+ vmv.v.x v8, t2
+ vsetvli zero, t0, e8, m4, ta, ma
+ vwaddu.wv v8, v8, v0
+ vsetvli zero, t0, e16, m8, ta, ma
+ vmax.vx v8, v8, zero
+ vsetvli zero, t0, e8, m4, ta, ma
+ vnclipu.wi v0, v8, 0
+ vsetivli zero, 8, e8, mf2, ta, ma
+ vsse64.v v0, (a0), a1
+ ret
+endfunc
+
+func ff_vc1_inv_trans_4x8_dc_rvv, zve32x
+ lh t2, (a2)
+ li t1, 17
+ mul t2, t2, t1
+ addi t2, t2, 4
+ srai t2, t2, 3
+ li t1, 12
+ mul t2, t2, t1
+ addi t2, t2, 64
+ srai t2, t2, 7
+ vsetivli zero, 8, e8, mf2, ta, ma
+ vlse32.v v0, (a0), a1
+ li t0, 4*8
+ vsetvli zero, t0, e16, m4, ta, ma
+ vmv.v.x v4, t2
+ vsetvli zero, t0, e8, m2, ta, ma
+ vwaddu.wv v4, v4, v0
+ vsetvli zero, t0, e16, m4, ta, ma
+ vmax.vx v4, v4, zero
+ vsetvli zero, t0, e8, m2, ta, ma
+ vnclipu.wi v0, v4, 0
+ vsetivli zero, 8, e8, mf2, ta, ma
+ vsse32.v v0, (a0), a1
+ ret
+endfunc
+
+func ff_vc1_inv_trans_8x4_dc_rvv, zve64x
+ lh t2, (a2)
+ li t1, 3
+ mul t2, t2, t1
+ addi t2, t2, 1
+ srai t2, t2, 1
+ li t1, 17
+ mul t2, t2, t1
+ addi t2, t2, 64
+ srai t2, t2, 7
+ vsetivli zero, 8, e8, mf2, ta, ma
+ vlse64.v v0, (a0), a1
+ li t0, 8*4
+ vsetvli zero, t0, e16, m4, ta, ma
+ vmv.v.x v4, t2
+ vsetvli zero, t0, e8, m2, ta, ma
+ vwaddu.wv v4, v4, v0
+ vsetvli zero, t0, e16, m4, ta, ma
+ vmax.vx v4, v4, zero
+ vsetvli zero, t0, e8, m2, ta, ma
+ vnclipu.wi v0, v4, 0
+ vsetivli zero, 8, e8, mf2, ta, ma
+ vsse64.v v0, (a0), a1
+ ret
+endfunc
+
+func ff_vc1_inv_trans_4x4_dc_rvv, zve32x
+ lh t2, (a2)
+ li t1, 17
+ mul t2, t2, t1
+ addi t2, t2, 4
+ srai t2, t2, 3
+ mul t2, t2, t1
+ addi t2, t2, 64
+ srai t2, t2, 7
+ vsetivli zero, 4, e8, mf2, ta, ma
+ vlse32.v v0, (a0), a1
+ li t0, 4*4
+ vsetvli zero, t0, e16, m2, ta, ma
+ vmv.v.x v2, t2
+ vsetvli zero, t0, e8, m1, ta, ma
+ vwaddu.wv v2, v2, v0
+ vsetvli zero, t0, e16, m2, ta, ma
+ vmax.vx v2, v2, zero
+ vsetvli zero, t0, e8, m1, ta, ma
+ vnclipu.wi v0, v2, 0
+ vsetivli zero, 4, e8, mf2, ta, ma
+ vsse32.v v0, (a0), a1
+ ret
+endfunc
diff --git a/libavcodec/vc1dsp.c b/libavcodec/vc1dsp.c
index 62c8eb21fa..2caa3c6863 100644
--- a/libavcodec/vc1dsp.c
+++ b/libavcodec/vc1dsp.c
@@ -1039,6 +1039,8 @@ av_cold void ff_vc1dsp_init(VC1DSPContext *dsp)
ff_vc1dsp_init_arm(dsp);
#elif ARCH_PPC
ff_vc1dsp_init_ppc(dsp);
+#elif ARCH_RISCV
+ ff_vc1dsp_init_riscv(dsp);
#elif ARCH_X86
ff_vc1dsp_init_x86(dsp);
#elif ARCH_MIPS
diff --git a/libavcodec/vc1dsp.h b/libavcodec/vc1dsp.h
index 7ed1776ca7..e3b90d2b62 100644
--- a/libavcodec/vc1dsp.h
+++ b/libavcodec/vc1dsp.h
@@ -89,6 +89,7 @@ void ff_vc1dsp_init(VC1DSPContext* c);
void ff_vc1dsp_init_aarch64(VC1DSPContext* dsp);
void ff_vc1dsp_init_arm(VC1DSPContext* dsp);
void ff_vc1dsp_init_ppc(VC1DSPContext *c);
+void ff_vc1dsp_init_riscv(VC1DSPContext *c);
void ff_vc1dsp_init_x86(VC1DSPContext* dsp);
void ff_vc1dsp_init_mips(VC1DSPContext* dsp);
void ff_vc1dsp_init_loongarch(VC1DSPContext* dsp);
--
2.43.0
c910 vc1dsp.vc1_inv_trans_4x4_dc_c: 84.0 vc1dsp.vc1_inv_trans_4x4_dc_rvv_i32: 74.0 vc1dsp.vc1_inv_trans_4x8_dc_c: 150.2 vc1dsp.vc1_inv_trans_4x8_dc_rvv_i32: 83.5 vc1dsp.vc1_inv_trans_8x4_dc_c: 129.0 vc1dsp.vc1_inv_trans_8x4_dc_rvv_i64: 75.7 vc1dsp.vc1_inv_trans_8x8_dc_c: 254.7 vc1dsp.vc1_inv_trans_8x8_dc_rvv_i64: 90.5