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[FFmpeg-devel,11/31] lavu/floatdsp: RISC-V V vector_dmul

Message ID 20220926145251.56351-11-remi@remlab.net
State Accepted
Commit da169a210dbd33d5d34baaf3d188ca5388b1b267
Headers show
Series initial RISC-V CPU extensions | expand

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Context Check Description
yinshiyou/make_loongarch64 success Make finished
yinshiyou/make_fate_loongarch64 success Make fate finished
andriy/make_x86 success Make finished
andriy/make_fate_x86 success Make fate finished

Commit Message

Rémi Denis-Courmont Sept. 26, 2022, 2:52 p.m. UTC 
From: Rémi Denis-Courmont <remi@remlab.net>

---
 libavutil/riscv/float_dsp_init.c |  6 +++++-
 libavutil/riscv/float_dsp_rvv.S  | 17 +++++++++++++++++
 2 files changed, 22 insertions(+), 1 deletion(-)
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Patch

diff --git a/libavutil/riscv/float_dsp_init.c b/libavutil/riscv/float_dsp_init.c
index 2482094ab4..29114dfb82 100644
--- a/libavutil/riscv/float_dsp_init.c
+++ b/libavutil/riscv/float_dsp_init.c
@@ -30,6 +30,8 @@  void ff_vector_fmul_rvv(float *dst, const float *src0, const float *src1,
 void ff_vector_fmul_scalar_rvv(float *dst, const float *src, float mul,
                                 int len);
 
+void ff_vector_dmul_rvv(double *dst, const double *src0, const double *src1,
+                         int len);
 void ff_vector_dmul_scalar_rvv(double *dst, const double *src, double mul,
                                 int len);
 
@@ -43,7 +45,9 @@  av_cold void ff_float_dsp_init_riscv(AVFloatDSPContext *fdsp)
         fdsp->vector_fmul_scalar = ff_vector_fmul_scalar_rvv;
     }
 
-    if (flags & AV_CPU_FLAG_RVV_F64)
+    if (flags & AV_CPU_FLAG_RVV_F64) {
+        fdsp->vector_dmul = ff_vector_dmul_rvv;
         fdsp->vector_dmul_scalar = ff_vector_dmul_scalar_rvv;
+    }
 #endif
 }
diff --git a/libavutil/riscv/float_dsp_rvv.S b/libavutil/riscv/float_dsp_rvv.S
index 00fb7354bb..710e122444 100644
--- a/libavutil/riscv/float_dsp_rvv.S
+++ b/libavutil/riscv/float_dsp_rvv.S
@@ -55,6 +55,23 @@  NOHWF   mv       a2, a3
         ret
 endfunc
 
+// (a0) = (a1) * (a2) [0..a3-1]
+func ff_vector_dmul_rvv, zve64d
+1:
+        vsetvli  t0, a3, e64, m1, ta, ma
+        vle64.v  v16, (a1)
+        sub      a3, a3, t0
+        vle64.v  v24, (a2)
+        sh3add   a1, t0, a1
+        vfmul.vv v16, v16, v24
+        sh3add   a2, t0, a2
+        vse64.v  v16, (a0)
+        sh3add   a0, t0, a0
+        bnez     a3, 1b
+
+        ret
+endfunc
+
 // (a0) = (a1) * fa0 [0..a2-1]
 func ff_vector_dmul_scalar_rvv, zve64d
 NOHWD   fmv.d.x  fa0, a2