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[FFmpeg-devel,09/31] lavu/floatdsp: RISC-V V vector_dmul_scalar

Message ID 20220926145251.56351-9-remi@remlab.net
State Accepted
Commit 89b7ec65a8c50a88ca730c666410f5743f600634
Headers show
Series initial RISC-V CPU extensions | expand

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Context Check Description
yinshiyou/make_loongarch64 success Make finished
yinshiyou/make_fate_loongarch64 success Make fate finished
andriy/make_x86 success Make finished
andriy/make_fate_x86 success Make fate finished

Commit Message

Rémi Denis-Courmont Sept. 26, 2022, 2:52 p.m. UTC 
From: Rémi Denis-Courmont <remi@remlab.net>

---
 libavutil/riscv/float_dsp_init.c |  6 ++++++
 libavutil/riscv/float_dsp_rvv.S  | 17 +++++++++++++++++
 2 files changed, 23 insertions(+)
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Patch

diff --git a/libavutil/riscv/float_dsp_init.c b/libavutil/riscv/float_dsp_init.c
index f4299049b0..3386139d49 100644
--- a/libavutil/riscv/float_dsp_init.c
+++ b/libavutil/riscv/float_dsp_init.c
@@ -28,6 +28,9 @@ 
 void ff_vector_fmul_scalar_rvv(float *dst, const float *src, float mul,
                                 int len);
 
+void ff_vector_dmul_scalar_rvv(double *dst, const double *src, double mul,
+                                int len);
+
 av_cold void ff_float_dsp_init_riscv(AVFloatDSPContext *fdsp)
 {
 #if HAVE_RVV
@@ -35,5 +38,8 @@  av_cold void ff_float_dsp_init_riscv(AVFloatDSPContext *fdsp)
 
     if (flags & AV_CPU_FLAG_RVV_F32)
         fdsp->vector_fmul_scalar = ff_vector_fmul_scalar_rvv;
+
+    if (flags & AV_CPU_FLAG_RVV_F64)
+        fdsp->vector_dmul_scalar = ff_vector_dmul_scalar_rvv;
 #endif
 }
diff --git a/libavutil/riscv/float_dsp_rvv.S b/libavutil/riscv/float_dsp_rvv.S
index 50cb1fa90f..17dda471b4 100644
--- a/libavutil/riscv/float_dsp_rvv.S
+++ b/libavutil/riscv/float_dsp_rvv.S
@@ -37,3 +37,20 @@  NOHWF   mv       a2, a3
 
         ret
 endfunc
+
+// (a0) = (a1) * fa0 [0..a2-1]
+func ff_vector_dmul_scalar_rvv, zve64d
+NOHWD   fmv.d.x  fa0, a2
+NOHWD   mv       a2, a3
+1:
+        vsetvli  t0, a2, e64, m1, ta, ma
+        vle64.v  v16, (a1)
+        sub      a2, a2, t0
+        vfmul.vf v16, v16, fa0
+        sh3add   a1, t0, a1
+        vse64.v  v16, (a0)
+        sh3add   a0, t0, a0
+        bnez     a2, 1b
+
+        ret
+endfunc