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[FFmpeg-devel,1/4] lavu/riscv: CPU flag for the Zbb extension

Message ID 20221002115501.17996-1-remi@remlab.net
State Accepted
Commit 37d5ddc317c35bded22fee8d79020653781d8230
Headers show
Series RISC-V initial bswapdsp | expand

Checks

Context Check Description
andriy/make_x86 success Make finished
andriy/make_fate_x86 success Make fate finished

Commit Message

Rémi Denis-Courmont Oct. 2, 2022, 11:54 a.m. UTC 
From: Rémi Denis-Courmont <remi@remlab.net>

Unfortunately, it is common, and will remain so, that the Bit
manipulations are not enabled at compilation time. This is an official
policy for Debian ports in general (though they do not support RISC-V
officially as of yet) to stick to the minimal target baseline, which
does not include the B extension or even its Zbb subset.

For inline helpers (CPOP, REV8), compiler builtins (CTZ, CLZ) or
even plain C code (MIN, MAX, MINU, MAXU), run-time detection seems
impractical. But at least it can work for the byte-swap DSP functions.
---
 libavutil/cpu.c           | 1 +
 libavutil/cpu.h           | 1 +
 libavutil/riscv/cpu.c     | 6 ++++++
 tests/checkasm/checkasm.c | 1 +
 4 files changed, 9 insertions(+)
diff mbox series

Patch

diff --git a/libavutil/cpu.c b/libavutil/cpu.c
index 5818fd9c1c..2c5f7f4958 100644
--- a/libavutil/cpu.c
+++ b/libavutil/cpu.c
@@ -188,6 +188,7 @@  int av_parse_cpu_caps(unsigned *flags, const char *s)
         { "rvv-f32",  NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_RVV_F32 },     .unit = "flags" },
         { "rvv-i64",  NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_RVV_I64 },     .unit = "flags" },
         { "rvv",      NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_RVV_F64 },     .unit = "flags" },
+        { "rvb-basic",NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_RVB_BASIC },   .unit = "flags" },
 #endif
         { NULL },
     };
diff --git a/libavutil/cpu.h b/libavutil/cpu.h
index 18f42af015..8fa5ea9199 100644
--- a/libavutil/cpu.h
+++ b/libavutil/cpu.h
@@ -86,6 +86,7 @@ 
 #define AV_CPU_FLAG_RVV_F32      (1 << 4) ///< Vectors of float's */
 #define AV_CPU_FLAG_RVV_I64      (1 << 5) ///< Vectors of 64-bit int's */
 #define AV_CPU_FLAG_RVV_F64      (1 << 6) ///< Vectors of double's
+#define AV_CPU_FLAG_RVB_BASIC    (1 << 7) ///< Basic bit-manipulations
 
 /**
  * Return the flags which specify extensions supported by the CPU.
diff --git a/libavutil/riscv/cpu.c b/libavutil/riscv/cpu.c
index e234201395..a9263dbb78 100644
--- a/libavutil/riscv/cpu.c
+++ b/libavutil/riscv/cpu.c
@@ -40,6 +40,8 @@  int ff_get_cpu_flags_riscv(void)
         ret |= AV_CPU_FLAG_RVF;
     if (hwcap & HWCAP_RV('D'))
         ret |= AV_CPU_FLAG_RVD;
+    if (hwcap & HWCAP_RV('B'))
+        ret |= AV_CPU_FLAG_RVB_BASIC;
 
     /* The V extension implies all Zve* functional subsets */
     if (hwcap & HWCAP_RV('V'))
@@ -57,6 +59,10 @@  int ff_get_cpu_flags_riscv(void)
 #endif
 #endif
 
+#ifdef __riscv_zbb
+    ret |= AV_CPU_FLAG_RVB_BASIC;
+#endif
+
     /* If RV-V is enabled statically at compile-time, check the details. */
 #ifdef __riscv_vectors
     ret |= AV_CPU_FLAG_RVV_I32;
diff --git a/tests/checkasm/checkasm.c b/tests/checkasm/checkasm.c
index 90dd7e4634..421bd096c5 100644
--- a/tests/checkasm/checkasm.c
+++ b/tests/checkasm/checkasm.c
@@ -240,6 +240,7 @@  static const struct {
     { "RVVf32",   "rvv_f32",  AV_CPU_FLAG_RVV_F32 },
     { "RVVi64",   "rvv_i64",  AV_CPU_FLAG_RVV_I64 },
     { "RVVf64",   "rvv_f64",  AV_CPU_FLAG_RVV_F64 },
+    { "RVBbasic", "rvb_b",    AV_CPU_FLAG_RVB_BASIC },
 #elif ARCH_MIPS
     { "MMI",      "mmi",      AV_CPU_FLAG_MMI },
     { "MSA",      "msa",      AV_CPU_FLAG_MSA },