diff mbox series

[FFmpeg-devel,3/4] lavu/fixed_dsp: R-V V vector_fmul

Message ID 20231004195110.38615-3-remi@remlab.net
State Accepted
Commit 10eb3b9c9f9e4175d63e6e1e8418b73eb49601f4
Headers show
Series [FFmpeg-devel,1/4] lavu/fixed_dsp: R-V V vector_fmul_add | expand

Checks

Context Check Description
yinshiyou/configure_loongarch64 warning Failed to apply patch

Commit Message

Rémi Denis-Courmont Oct. 4, 2023, 7:51 p.m. UTC 
vector_fmul_fixed_c: 4.0
vector_fmul_fixed_rvv_i64: 0.5
---
 libavutil/riscv/fixed_dsp_init.c |  3 +++
 libavutil/riscv/fixed_dsp_rvv.S  | 17 +++++++++++++++++
 2 files changed, 20 insertions(+)
diff mbox series

Patch

diff --git a/libavutil/riscv/fixed_dsp_init.c b/libavutil/riscv/fixed_dsp_init.c
index 470b35fb63..02883b31d4 100644
--- a/libavutil/riscv/fixed_dsp_init.c
+++ b/libavutil/riscv/fixed_dsp_init.c
@@ -25,6 +25,8 @@ 
 #include "libavutil/cpu.h"
 #include "libavutil/fixed_dsp.h"
 
+void ff_vector_fmul_fixed_rvv(int *dst, const int *src0, const int *src1,
+                              int len);
 void ff_vector_fmul_reverse_fixed_rvv(int *dst, const int *src0,
                                       const int *src1, int len);
 void ff_vector_fmul_add_fixed_rvv(int *dst, const int *src0, const int *src1,
@@ -38,6 +40,7 @@  av_cold void ff_fixed_dsp_init_riscv(AVFixedDSPContext *fdsp)
     int flags = av_get_cpu_flags();
 
     if ((flags & AV_CPU_FLAG_RVV_I32) && (flags & AV_CPU_FLAG_RVB_ADDR)) {
+        fdsp->vector_fmul = ff_vector_fmul_fixed_rvv;
         fdsp->vector_fmul_reverse = ff_vector_fmul_reverse_fixed_rvv;
         fdsp->vector_fmul_add = ff_vector_fmul_add_fixed_rvv;
 
diff --git a/libavutil/riscv/fixed_dsp_rvv.S b/libavutil/riscv/fixed_dsp_rvv.S
index 8a5d1853c5..d5d538239f 100644
--- a/libavutil/riscv/fixed_dsp_rvv.S
+++ b/libavutil/riscv/fixed_dsp_rvv.S
@@ -20,6 +20,23 @@ 
 
 #include "asm.S"
 
+func ff_vector_fmul_fixed_rvv, zve32x
+        csrwi   vxrm, 0
+1:
+        vsetvli t0, a3, e32, m4, ta, ma
+        vle32.v v16, (a1)
+        sub     a3, a3, t0
+        vle32.v v24, (a2)
+        sh2add  a1, t0, a1
+        vsmul.vv v8, v16, v24
+        sh2add  a2, t0, a2
+        vse32.v v8, (a0)
+        sh2add  a0, t0, a0
+        bnez    a3, 1b
+
+        ret
+endfunc
+
 func ff_vector_fmul_reverse_fixed_rvv, zve32x
         csrwi   vxrm, 0
         vsetvli t0, zero, e16, m4, ta, ma