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[FFmpeg-devel,13/31] lavu/floatdsp: RISC-V V vector_dmac_scalar

Message ID 20220926145251.56351-13-remi@remlab.net
State Accepted
Commit d120ab5b915fb422247f9e4dd5b823d1b47d6adf
Headers show
Series initial RISC-V CPU extensions | expand

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Context Check Description
yinshiyou/make_loongarch64 success Make finished
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andriy/make_x86 success Make finished
andriy/make_fate_x86 success Make fate finished

Commit Message

Rémi Denis-Courmont Sept. 26, 2022, 2:52 p.m. UTC 
From: Rémi Denis-Courmont <remi@remlab.net>

---
 libavutil/riscv/float_dsp_init.c |  3 +++
 libavutil/riscv/float_dsp_rvv.S  | 18 ++++++++++++++++++
 2 files changed, 21 insertions(+)
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Patch

diff --git a/libavutil/riscv/float_dsp_init.c b/libavutil/riscv/float_dsp_init.c
index 9e19413d5d..a559bbb32b 100644
--- a/libavutil/riscv/float_dsp_init.c
+++ b/libavutil/riscv/float_dsp_init.c
@@ -34,6 +34,8 @@  void ff_vector_fmul_scalar_rvv(float *dst, const float *src, float mul,
 
 void ff_vector_dmul_rvv(double *dst, const double *src0, const double *src1,
                          int len);
+void ff_vector_dmac_scalar_rvv(double *dst, const double *src, double mul,
+                                int len);
 void ff_vector_dmul_scalar_rvv(double *dst, const double *src, double mul,
                                 int len);
 
@@ -50,6 +52,7 @@  av_cold void ff_float_dsp_init_riscv(AVFloatDSPContext *fdsp)
 
     if (flags & AV_CPU_FLAG_RVV_F64) {
         fdsp->vector_dmul = ff_vector_dmul_rvv;
+        fdsp->vector_dmac_scalar = ff_vector_dmac_scalar_rvv;
         fdsp->vector_dmul_scalar = ff_vector_dmul_scalar_rvv;
     }
 #endif
diff --git a/libavutil/riscv/float_dsp_rvv.S b/libavutil/riscv/float_dsp_rvv.S
index 4c325db9fd..048ec0bc40 100644
--- a/libavutil/riscv/float_dsp_rvv.S
+++ b/libavutil/riscv/float_dsp_rvv.S
@@ -91,6 +91,24 @@  func ff_vector_dmul_rvv, zve64d
         ret
 endfunc
 
+// (a0) += (a1) * fa0 [0..a2-1]
+func ff_vector_dmac_scalar_rvv, zve64d
+NOHWD   fmv.d.x   fa0, a2
+NOHWD   mv        a2, a3
+1:
+        vsetvli   t0, a2, e64, m1, ta, ma
+        vle64.v   v24, (a1)
+        sub       a2, a2, t0
+        vle64.v   v16, (a0)
+        sh3add    a1, t0, a1
+        vfmacc.vf v16, fa0, v24
+        vse64.v   v16, (a0)
+        sh3add    a0, t0, a0
+        bnez      a2, 1b
+
+        ret
+endfunc
+
 // (a0) = (a1) * fa0 [0..a2-1]
 func ff_vector_dmul_scalar_rvv, zve64d
 NOHWD   fmv.d.x  fa0, a2